Enables more VM tests for SIMMIPS.

runtime/vm/assembler_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_MIPS)
 
 #include "vm/assembler.h"
 #include "vm/runtime_entry.h"
 #include "vm/simulator.h"
@@ skipping 317 matching lines @@
   const intptr_t table_offset_in_isolate =
       Isolate::class_table_offset() + ClassTable::table_offset();
   lw(result, Address(result, table_offset_in_isolate));
   sll(TMP1, TMP1, 2);
   addu(result, result, TMP1);
   lw(result, Address(result));
 }
 
 
 void Assembler::EnterStubFrame(bool uses_pp) {
+  SetPrologueOffset();
   if (uses_pp) {
     addiu(SP, SP, Immediate(-4 * kWordSize));
     sw(ZR, Address(SP, 3 * kWordSize));  // PC marker is 0 in stubs.
     sw(RA, Address(SP, 2 * kWordSize));
     sw(FP, Address(SP, 1 * kWordSize));
     sw(PP, Address(SP, 0 * kWordSize));
     addiu(FP, SP, Immediate(1 * kWordSize));
     // Setup pool pointer for this stub.
     Label next;
     bal(&next);
@@ skipping 87 matching lines @@
 
 
 void Assembler::CallRuntime(const RuntimeEntry& entry) {
   entry.Call(this);
 }
 
 
 void Assembler::EnterDartFrame(intptr_t frame_size) {
   const intptr_t offset = CodeSize();
 
+  SetPrologueOffset();
+
   addiu(SP, SP, Immediate(-4 * kWordSize));
   sw(RA, Address(SP, 2 * kWordSize));
   sw(FP, Address(SP, 1 * kWordSize));
   sw(PP, Address(SP, 0 * kWordSize));
 
   Label next;
   // Branch and link to the instruction after the delay slot to get the PC.
   bal(&next);
   // RA is the address of the sw instruction below. Save it in T0.
-  delay_slot()->mov(T0, RA);
+  delay_slot()->mov(TMP1, RA);
 
   // Calculate the offset of the pool pointer from the PC.
   const intptr_t object_pool_pc_dist =
       Instructions::HeaderSize() - Instructions::object_pool_offset() +
       CodeSize();
 
   // This sw instruction is the return address for the bal, so T0 holds
   // the PC at this sw instruction.
   Bind(&next);
 
   // Save PC in frame for fast identification of corresponding code.
   if (offset == 0) {
-    sw(T0, Address(SP, 3 * kWordSize));
+    sw(TMP1, Address(SP, 3 * kWordSize));
   } else {
     // Adjust saved PC for any intrinsic code that could have been generated
     // before a frame is created.
-    AddImmediate(T1, T0, -offset);
-    sw(T1, Address(SP, 3 * kWordSize));
+    addiu(TMP1, TMP1, Immediate(-offset));
+    sw(TMP1, Address(SP, 3 * kWordSize));
   }
 
   // Set FP to the saved previous FP.
   addiu(FP, SP, Immediate(kWordSize));
 
-  // Load the pool pointer.
-  lw(PP, Address(T0, -object_pool_pc_dist));
+  // Load the pool pointer. offset has already been subtracted from TMP1.
+  lw(PP, Address(TMP1, -object_pool_pc_dist + offset));
 
   // Reserve space for locals.
   AddImmediate(SP, -frame_size);
 }
 
 
 void Assembler::LeaveDartFrameAndReturn() {
   addiu(SP, FP, Immediate(-kWordSize));
 
   lw(RA, Address(SP, 2 * kWordSize));
@@ skipping 16 matching lines @@
   }
 }
 
 
 void Assembler::EnterCallRuntimeFrame(intptr_t frame_space) {
   const intptr_t kPushedRegistersSize =
       kDartVolatileCpuRegCount * kWordSize +
       2 * kWordSize +  // FP and RA.
       kDartVolatileFpuRegCount * kWordSize;
 
+  SetPrologueOffset();
+
   TraceSimMsg("EnterCallRuntimeFrame");
 
-  if (prologue_offset_ == -1) {
-    prologue_offset_ = CodeSize();
-  }
-
   // Save volatile CPU and FPU registers on the stack:
   // -------------
   // FPU Registers
   // CPU Registers
   // RA
   // FP
   // -------------
   // TODO(zra): It may be a problem for walking the stack that FP is below
   //            the saved registers. If it turns out to be a problem in the
   //            future, try pushing RA and FP before the volatile registers.
@@ skipping 62 matching lines @@
   ASSERT(Utils::IsAligned(address, 4));
   // The address is stored in the object array as a RawSmi.
   const Smi& smi = Smi::Handle(Smi::New(address >> kSmiTagShift));
   // Do not reuse an existing entry, since each reference may be patched
   // independently.
   object_pool_.Add(smi, Heap::kOld);
   return object_pool_.Length() - 1;
 }
 
 
+static const char* cpu_reg_names[kNumberOfCpuRegisters] = {
+  "zr", "tmp", "v0", "v1", "a0", "a1", "a2", "a3",
+  "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
+  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
+  "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
+};
+
+
+const char* Assembler::RegisterName(Register reg) {
+  ASSERT((0 <= reg) && (reg < kNumberOfCpuRegisters));
+  return cpu_reg_names[reg];
+}
+
+
+static const char* fpu_reg_names[kNumberOfFpuRegisters] = {
+  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
+  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
+};
+
+
+const char* Assembler::FpuRegisterName(FpuRegister reg) {
+  ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
+  return fpu_reg_names[reg];
+}
+
+
 void Assembler::Stop(const char* message) {
   if (FLAG_print_stop_message) {
     UNIMPLEMENTED();
   }
   Label stop;
   b(&stop);
   Emit(reinterpret_cast<int32_t>(message));
   Bind(&stop);
   break_(Instr::kStopMessageCode);
 }
@@ skipping 10 matching lines @@
     Bind(&msg);
     break_(Instr::kMsgMessageCode);
   }
 #endif
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS