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Unified Diff: src/x64/assembler-x64.cc

Issue 1593313010: Revert of [turbofan] Implement rounding of floats on x64 and ia32 without sse4.1. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 4 years, 11 months ago
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Index: src/x64/assembler-x64.cc
diff --git a/src/x64/assembler-x64.cc b/src/x64/assembler-x64.cc
index 05c4d676418bbfb870460e852764e48220fd727b..3cf3398e876e3a51e291a2e2f60ca88355e8d87b 100644
--- a/src/x64/assembler-x64.cc
+++ b/src/x64/assembler-x64.cc
@@ -3130,190 +3130,168 @@
emit(0xF3);
emit_rex_64(dst, src);
emit(0x0F);
- emit(0x2D);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvtss2siq(Register dst, XMMRegister src) {
+ emit(0x2C);
+ emit_sse_operand(dst, src);
+}
+
+
+void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
+ DCHECK(!IsEnabled(AVX));
+ EnsureSpace ensure_space(this);
+ emit(0xF2);
+ emit_rex_64(dst, src);
+ emit(0x0F);
+ emit(0x2C);
+ emit_sse_operand(dst, src);
+}
+
+
+void Assembler::cvttsd2siq(Register dst, const Operand& src) {
+ DCHECK(!IsEnabled(AVX));
+ EnsureSpace ensure_space(this);
+ emit(0xF2);
+ emit_rex_64(dst, src);
+ emit(0x0F);
+ emit(0x2C);
+ emit_sse_operand(dst, src);
+}
+
+
+void Assembler::cvtlsi2sd(XMMRegister dst, const Operand& src) {
+ DCHECK(!IsEnabled(AVX));
+ EnsureSpace ensure_space(this);
+ emit(0xF2);
+ emit_optional_rex_32(dst, src);
+ emit(0x0F);
+ emit(0x2A);
+ emit_sse_operand(dst, src);
+}
+
+
+void Assembler::cvtlsi2sd(XMMRegister dst, Register src) {
+ DCHECK(!IsEnabled(AVX));
+ EnsureSpace ensure_space(this);
+ emit(0xF2);
+ emit_optional_rex_32(dst, src);
+ emit(0x0F);
+ emit(0x2A);
+ emit_sse_operand(dst, src);
+}
+
+
+void Assembler::cvtlsi2ss(XMMRegister dst, const Operand& src) {
+ DCHECK(!IsEnabled(AVX));
+ EnsureSpace ensure_space(this);
+ emit(0xF3);
+ emit_optional_rex_32(dst, src);
+ emit(0x0F);
+ emit(0x2A);
+ emit_sse_operand(dst, src);
+}
+
+
+void Assembler::cvtlsi2ss(XMMRegister dst, Register src) {
+ EnsureSpace ensure_space(this);
+ emit(0xF3);
+ emit_optional_rex_32(dst, src);
+ emit(0x0F);
+ emit(0x2A);
+ emit_sse_operand(dst, src);
+}
+
+
+void Assembler::cvtqsi2ss(XMMRegister dst, const Operand& src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF3);
emit_rex_64(dst, src);
emit(0x0F);
- emit(0x2D);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvtss2siq(Register dst, const Operand& src) {
+ emit(0x2A);
+ emit_sse_operand(dst, src);
+}
+
+
+void Assembler::cvtqsi2ss(XMMRegister dst, Register src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF3);
emit_rex_64(dst, src);
emit(0x0F);
- emit(0x2C);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
+ emit(0x2A);
+ emit_sse_operand(dst, src);
+}
+
+
+void Assembler::cvtqsi2sd(XMMRegister dst, const Operand& src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2);
emit_rex_64(dst, src);
emit(0x0F);
- emit(0x2C);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvttsd2siq(Register dst, const Operand& src) {
+ emit(0x2A);
+ emit_sse_operand(dst, src);
+}
+
+
+void Assembler::cvtqsi2sd(XMMRegister dst, Register src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2);
emit_rex_64(dst, src);
emit(0x0F);
- emit(0x2C);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvtlsi2sd(XMMRegister dst, const Operand& src) {
+ emit(0x2A);
+ emit_sse_operand(dst, src);
+}
+
+
+void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
+ DCHECK(!IsEnabled(AVX));
+ EnsureSpace ensure_space(this);
+ emit(0xF3);
+ emit_optional_rex_32(dst, src);
+ emit(0x0F);
+ emit(0x5A);
+ emit_sse_operand(dst, src);
+}
+
+
+void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) {
+ DCHECK(!IsEnabled(AVX));
+ EnsureSpace ensure_space(this);
+ emit(0xF3);
+ emit_optional_rex_32(dst, src);
+ emit(0x0F);
+ emit(0x5A);
+ emit_sse_operand(dst, src);
+}
+
+
+void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
- emit(0x2A);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvtlsi2sd(XMMRegister dst, Register src) {
+ emit(0x5A);
+ emit_sse_operand(dst, src);
+}
+
+
+void Assembler::cvtsd2ss(XMMRegister dst, const Operand& src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
- emit(0x2A);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvtlsi2ss(XMMRegister dst, const Operand& src) {
- DCHECK(!IsEnabled(AVX));
- EnsureSpace ensure_space(this);
- emit(0xF3);
- emit_optional_rex_32(dst, src);
- emit(0x0F);
- emit(0x2A);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvtlsi2ss(XMMRegister dst, Register src) {
- EnsureSpace ensure_space(this);
- emit(0xF3);
- emit_optional_rex_32(dst, src);
- emit(0x0F);
- emit(0x2A);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvtqsi2ss(XMMRegister dst, const Operand& src) {
- DCHECK(!IsEnabled(AVX));
- EnsureSpace ensure_space(this);
- emit(0xF3);
- emit_rex_64(dst, src);
- emit(0x0F);
- emit(0x2A);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvtqsi2ss(XMMRegister dst, Register src) {
- DCHECK(!IsEnabled(AVX));
- EnsureSpace ensure_space(this);
- emit(0xF3);
- emit_rex_64(dst, src);
- emit(0x0F);
- emit(0x2A);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvtqsi2sd(XMMRegister dst, const Operand& src) {
+ emit(0x5A);
+ emit_sse_operand(dst, src);
+}
+
+
+void Assembler::cvtsd2si(Register dst, XMMRegister src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2);
- emit_rex_64(dst, src);
- emit(0x0F);
- emit(0x2A);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvtqsi2sd(XMMRegister dst, Register src) {
- DCHECK(!IsEnabled(AVX));
- EnsureSpace ensure_space(this);
- emit(0xF2);
- emit_rex_64(dst, src);
- emit(0x0F);
- emit(0x2A);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
- DCHECK(!IsEnabled(AVX));
- EnsureSpace ensure_space(this);
- emit(0xF3);
- emit_optional_rex_32(dst, src);
- emit(0x0F);
- emit(0x5A);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) {
- DCHECK(!IsEnabled(AVX));
- EnsureSpace ensure_space(this);
- emit(0xF3);
- emit_optional_rex_32(dst, src);
- emit(0x0F);
- emit(0x5A);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
- DCHECK(!IsEnabled(AVX));
- EnsureSpace ensure_space(this);
- emit(0xF2);
- emit_optional_rex_32(dst, src);
- emit(0x0F);
- emit(0x5A);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvtsd2ss(XMMRegister dst, const Operand& src) {
- DCHECK(!IsEnabled(AVX));
- EnsureSpace ensure_space(this);
- emit(0xF2);
- emit_optional_rex_32(dst, src);
- emit(0x0F);
- emit(0x5A);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvtsd2si(Register dst, XMMRegister src) {
- DCHECK(!IsEnabled(AVX));
- EnsureSpace ensure_space(this);
- emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x2D);
@@ -3322,17 +3300,6 @@
void Assembler::cvtsd2siq(Register dst, XMMRegister src) {
- DCHECK(!IsEnabled(AVX));
- EnsureSpace ensure_space(this);
- emit(0xF2);
- emit_rex_64(dst, src);
- emit(0x0F);
- emit(0x2D);
- emit_sse_operand(dst, src);
-}
-
-
-void Assembler::cvtsd2siq(Register dst, const Operand& src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit(0xF2);
@@ -3576,22 +3543,6 @@
emit_sse_operand(dst, src);
// Mask precision exception.
emit(static_cast<byte>(mode) | 0x8);
-}
-
-
-void Assembler::ldmxcsr(const Operand& dst) {
- EnsureSpace ensure_space(this);
- emit(0x0F);
- emit(0xAE);
- emit_operand(2, dst);
-}
-
-
-void Assembler::stmxcsr(const Operand& dst) {
- EnsureSpace ensure_space(this);
- emit(0x0F);
- emit(0xAE);
- emit_operand(3, dst);
}
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