Subzero. ARM32. Fixes vpush/vpop bug.

pydir/gen_arm32_reg_tables.py

 import os
 import sys
 
 class RegAliases(object):
   def __init__(self, AliasesStr):
     self.Aliases = list(Alias.strip() for Alias in AliasesStr.split(','))
 
   def __str__(self):
     return 'REGLIST{AliasCount}(RegARM32, {Aliases})'.format(
       AliasCount=len(self.Aliases), Aliases=', '.join(self.Aliases))
@@ skipping 176 matching lines @@
   Reg( 'q8',  8,   IsScratch=1,          IsVec128=1, Aliases= 'q8, d16, d17'),
   Reg( 'q9',  9,   IsScratch=1,          IsVec128=1, Aliases= 'q9, d18, d19'),
   Reg('q10', 10,   IsScratch=1,          IsVec128=1, Aliases='q10, d20, d21'),
   Reg('q11', 11,   IsScratch=1,          IsVec128=1, Aliases='q11, d22, d23'),
   Reg('q12', 12,   IsScratch=1,          IsVec128=1, Aliases='q12, d24, d25'),
   Reg('q13', 13,   IsScratch=1,          IsVec128=1, Aliases='q13, d26, d27'),
   Reg('q14', 14,   IsScratch=1,          IsVec128=1, Aliases='q14, d28, d29'),
   Reg('q15', 15,   IsScratch=1,          IsVec128=1, Aliases='q15, d30, d31'),
 ]
 
-def _reverse(x):
-  return sorted(x, key=lambda x: x.Encode, reverse=True)
-
-RegClasses = [('GPR', GPRs), ('I64PAIR', I64Pairs), ('FP32', FP32),
-              ('FP64', _reverse(FP64)), ('VEC128', _reverse(Vec128))]
+# TODO(jpp): Fix the pop emission, then emit FP64/Vec128 reverted.
+RegClasses = [('GPR', GPRs),  ('I64PAIR', I64Pairs), ('FP32', FP32),
+              ('FP64', FP64), ('VEC128', Vec128)]
 
 AllRegs = {}
 for _, RegClass in RegClasses:
   for Reg in RegClass:
     assert Reg.Name not in AllRegs
     AllRegs[Reg.Name] = Reg
 
 for _, RegClass in RegClasses:
   for Reg in RegClass:
     for Alias in AllRegs[Reg.Name].Features.Aliases().Aliases:
       assert AllRegs[Alias].IsAnAliasOf(Reg), '%s VS %s' % (Reg, AllRegs[Alias])
       assert (AllRegs[Alias].Features.LivesInGPR() ==
                  Reg.Features.LivesInGPR()), '%s VS %s' % (Reg, AllRegs[Alias])
       assert (AllRegs[Alias].Features.LivesInVFP() ==
                  Reg.Features.LivesInVFP()), '%s VS %s' % (Reg, AllRegs[Alias])
 
 print ("// This file was auto generated by the {script} script.\n"
        "// Do not modify it: modify the script instead.\n"
        "\n"
        "#ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF\n"
        "#define SUBZERO_SRC_ICEREGISTERSARM32_DEF\n".format(script=os.path.basename(sys.argv[0])))
 
 for Name, RegClass in RegClasses:
   print '\n//{xmacro}'.format(xmacro=Reg.DefiningXMacro())
   print "#define REGARM32_%s_TABLE" % Name,
   for Reg in RegClass:
     print '\\\n  X({Reg})'.format(Reg=Reg),
   print '\n'
 print "#endif // SUBZERO_SRC_ICEREGISTERSARM32_DEF",