Merge lowerCall and lowerRet between x86 and x64

src/IceTargetLoweringX86Base.h

 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 179 matching lines @@
 
   explicit TargetX86Base(Cfg *Func);
 
   void postLower() override;
 
   void initSandbox() {
     dispatchToConcrete(&Traits::ConcreteTarget::initSandbox);
   }
 
   void lowerAlloca(const InstAlloca *Inst) override;
+  void lowerArguments() override;
   void lowerArithmetic(const InstArithmetic *Inst) override;
   void lowerAssign(const InstAssign *Inst) override;
   void lowerBr(const InstBr *Inst) override;
+  void lowerCall(const InstCall *Inst) override;
   void lowerCast(const InstCast *Inst) override;
   void lowerExtractElement(const InstExtractElement *Inst) override;
   void lowerFcmp(const InstFcmp *Inst) override;
   void lowerIcmp(const InstIcmp *Inst) override;
 
   void lowerIntrinsicCall(const InstIntrinsicCall *Inst) override;
   void lowerInsertElement(const InstInsertElement *Inst) override;
   void lowerLoad(const InstLoad *Inst) override;
   void lowerPhi(const InstPhi *Inst) override;
+  void lowerRet(const InstRet *Inst) override;
   void lowerSelect(const InstSelect *Inst) override;
   void lowerStore(const InstStore *Inst) override;
   void lowerSwitch(const InstSwitch *Inst) override;
   void lowerUnreachable(const InstUnreachable *Inst) override;
   void lowerOther(const Inst *Instr) override;
   void lowerRMW(const InstX86FakeRMW *RMW);
   void prelowerPhis() override;
   uint32_t getCallStackArgumentsSizeBytes(const std::vector<Type> &ArgTypes,
                                           Type ReturnType);
   uint32_t getCallStackArgumentsSizeBytes(const InstCall *Instr) override;
@@ skipping 50 matching lines @@
 
   using LowerBinOp = void (TargetX86Base::*)(Variable *, Operand *);
   void expandAtomicRMWAsCmpxchg(LowerBinOp op_lo, LowerBinOp op_hi,
                                 Variable *Dest, Operand *Ptr, Operand *Val);
 
   void eliminateNextVectorSextInstruction(Variable *SignExtendedResult);
 
   void scalarizeArithmetic(InstArithmetic::OpKind K, Variable *Dest,
                            Operand *Src0, Operand *Src1);
 
+  /// Emit just the call instruction (without argument or return variable
+  /// processing), sandboxing if needed.
+  virtual Inst *emitCallToTarget(Operand *CallTarget, Variable *ReturnReg) = 0;
+  /// Materialize the moves needed to return a value of the specified type.
+  virtual Variable *moveReturnValueToRegister(Operand *Value,
+                                              Type ReturnType) = 0;
+
   /// Emit a fake use of esp to make sure esp stays alive for the entire
   /// function. Otherwise some esp adjustments get dead-code eliminated.
   void keepEspLiveAtExit() {
     Variable *esp =
         Func->getTarget()->getPhysicalRegister(getStackReg(), Traits::WordType);
     Context.insert<InstFakeUse>(esp);
   }
 
   /// Operand legalization helpers. To deal with address mode constraints, the
   /// helpers will create a new Operand and emit instructions that guarantee
@@ skipping 703 matching lines @@
 
   static FixupKind PcRelFixup;
   static FixupKind AbsFixup;
 };
 } // end of namespace X86NAMESPACE
 } // end of namespace Ice
 
 #include "IceTargetLoweringX86BaseImpl.h"
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H