OLD | NEW |
1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// | 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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2780 } | 2780 } |
2781 | 2781 |
2782 Operand *Src0 = legalizeUndef(Instr->getSrc(0)); | 2782 Operand *Src0 = legalizeUndef(Instr->getSrc(0)); |
2783 Operand *Src1 = legalizeUndef(Instr->getSrc(1)); | 2783 Operand *Src1 = legalizeUndef(Instr->getSrc(1)); |
2784 if (DestTy == IceType_i64) { | 2784 if (DestTy == IceType_i64) { |
2785 lowerInt64Arithmetic(Instr->getOp(), Instr->getDest(), Src0, Src1); | 2785 lowerInt64Arithmetic(Instr->getOp(), Instr->getDest(), Src0, Src1); |
2786 return; | 2786 return; |
2787 } | 2787 } |
2788 | 2788 |
2789 if (isVectorType(DestTy)) { | 2789 if (isVectorType(DestTy)) { |
2790 // Add a fake def to keep liveness consistent in the meantime. | 2790 UnimplementedLoweringError(this, Instr); |
2791 Variable *T = makeReg(DestTy); | |
2792 Context.insert<InstFakeDef>(T); | |
2793 _mov(Dest, T); | |
2794 UnimplementedError(Func->getContext()->getFlags()); | |
2795 return; | 2791 return; |
2796 } | 2792 } |
2797 | 2793 |
2798 // DestTy is a non-i64 scalar. | 2794 // DestTy is a non-i64 scalar. |
2799 Variable *T = makeReg(DestTy); | 2795 Variable *T = makeReg(DestTy); |
2800 | 2796 |
2801 // * Handle div/rem separately. They require a non-legalized Src1 to inspect | 2797 // * Handle div/rem separately. They require a non-legalized Src1 to inspect |
2802 // whether or not Src1 is a non-zero constant. Once legalized it is more | 2798 // whether or not Src1 is a non-zero constant. Once legalized it is more |
2803 // difficult to determine (constant may be moved to a register). | 2799 // difficult to determine (constant may be moved to a register). |
2804 // * Handle floating point arithmetic separately: they require Src1 to be | 2800 // * Handle floating point arithmetic separately: they require Src1 to be |
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3489 void TargetARM32::lowerCast(const InstCast *Inst) { | 3485 void TargetARM32::lowerCast(const InstCast *Inst) { |
3490 InstCast::OpKind CastKind = Inst->getCastKind(); | 3486 InstCast::OpKind CastKind = Inst->getCastKind(); |
3491 Variable *Dest = Inst->getDest(); | 3487 Variable *Dest = Inst->getDest(); |
3492 Operand *Src0 = legalizeUndef(Inst->getSrc(0)); | 3488 Operand *Src0 = legalizeUndef(Inst->getSrc(0)); |
3493 switch (CastKind) { | 3489 switch (CastKind) { |
3494 default: | 3490 default: |
3495 Func->setError("Cast type not supported"); | 3491 Func->setError("Cast type not supported"); |
3496 return; | 3492 return; |
3497 case InstCast::Sext: { | 3493 case InstCast::Sext: { |
3498 if (isVectorType(Dest->getType())) { | 3494 if (isVectorType(Dest->getType())) { |
3499 Variable *T = makeReg(Dest->getType()); | 3495 UnimplementedLoweringError(this, Inst); |
3500 Context.insert<InstFakeDef>(T, legalizeToReg(Src0)); | |
3501 _mov(Dest, T); | |
3502 UnimplementedError(Func->getContext()->getFlags()); | |
3503 } else if (Dest->getType() == IceType_i64) { | 3496 } else if (Dest->getType() == IceType_i64) { |
3504 // t1=sxtb src; t2= mov t1 asr #31; dst.lo=t1; dst.hi=t2 | 3497 // t1=sxtb src; t2= mov t1 asr #31; dst.lo=t1; dst.hi=t2 |
3505 Constant *ShiftAmt = Ctx->getConstantInt32(31); | 3498 Constant *ShiftAmt = Ctx->getConstantInt32(31); |
3506 auto *DestLo = llvm::cast<Variable>(loOperand(Dest)); | 3499 auto *DestLo = llvm::cast<Variable>(loOperand(Dest)); |
3507 auto *DestHi = llvm::cast<Variable>(hiOperand(Dest)); | 3500 auto *DestHi = llvm::cast<Variable>(hiOperand(Dest)); |
3508 Variable *T_Lo = makeReg(DestLo->getType()); | 3501 Variable *T_Lo = makeReg(DestLo->getType()); |
3509 if (Src0->getType() == IceType_i32) { | 3502 if (Src0->getType() == IceType_i32) { |
3510 Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex); | 3503 Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex); |
3511 _mov(T_Lo, Src0RF); | 3504 _mov(T_Lo, Src0RF); |
3512 } else if (Src0->getType() != IceType_i1) { | 3505 } else if (Src0->getType() != IceType_i1) { |
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3537 Constant *_0 = Ctx->getConstantZero(IceType_i32); | 3530 Constant *_0 = Ctx->getConstantZero(IceType_i32); |
3538 Operand *_m1 = Ctx->getConstantInt(Dest->getType(), -1); | 3531 Operand *_m1 = Ctx->getConstantInt(Dest->getType(), -1); |
3539 Variable *T = makeReg(Dest->getType()); | 3532 Variable *T = makeReg(Dest->getType()); |
3540 lowerInt1ForSelect(T, Src0, _m1, _0); | 3533 lowerInt1ForSelect(T, Src0, _m1, _0); |
3541 _mov(Dest, T); | 3534 _mov(Dest, T); |
3542 } | 3535 } |
3543 break; | 3536 break; |
3544 } | 3537 } |
3545 case InstCast::Zext: { | 3538 case InstCast::Zext: { |
3546 if (isVectorType(Dest->getType())) { | 3539 if (isVectorType(Dest->getType())) { |
3547 Variable *T = makeReg(Dest->getType()); | 3540 UnimplementedLoweringError(this, Inst); |
3548 Context.insert<InstFakeDef>(T, legalizeToReg(Src0)); | |
3549 _mov(Dest, T); | |
3550 UnimplementedError(Func->getContext()->getFlags()); | |
3551 } else if (Dest->getType() == IceType_i64) { | 3541 } else if (Dest->getType() == IceType_i64) { |
3552 // t1=uxtb src; dst.lo=t1; dst.hi=0 | 3542 // t1=uxtb src; dst.lo=t1; dst.hi=0 |
3553 Operand *_0 = | 3543 Operand *_0 = |
3554 legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex); | 3544 legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex); |
3555 auto *DestLo = llvm::cast<Variable>(loOperand(Dest)); | 3545 auto *DestLo = llvm::cast<Variable>(loOperand(Dest)); |
3556 auto *DestHi = llvm::cast<Variable>(hiOperand(Dest)); | 3546 auto *DestHi = llvm::cast<Variable>(hiOperand(Dest)); |
3557 Variable *T_Lo = makeReg(DestLo->getType()); | 3547 Variable *T_Lo = makeReg(DestLo->getType()); |
3558 | 3548 |
3559 switch (Src0->getType()) { | 3549 switch (Src0->getType()) { |
3560 default: { | 3550 default: { |
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3593 // t1 = uxt src; dst = t1 | 3583 // t1 = uxt src; dst = t1 |
3594 Variable *Src0R = legalizeToReg(Src0); | 3584 Variable *Src0R = legalizeToReg(Src0); |
3595 Variable *T = makeReg(Dest->getType()); | 3585 Variable *T = makeReg(Dest->getType()); |
3596 _uxt(T, Src0R); | 3586 _uxt(T, Src0R); |
3597 _mov(Dest, T); | 3587 _mov(Dest, T); |
3598 } | 3588 } |
3599 break; | 3589 break; |
3600 } | 3590 } |
3601 case InstCast::Trunc: { | 3591 case InstCast::Trunc: { |
3602 if (isVectorType(Dest->getType())) { | 3592 if (isVectorType(Dest->getType())) { |
3603 Variable *T = makeReg(Dest->getType()); | 3593 UnimplementedLoweringError(this, Inst); |
3604 Context.insert<InstFakeDef>(T, legalizeToReg(Src0)); | |
3605 _mov(Dest, T); | |
3606 UnimplementedError(Func->getContext()->getFlags()); | |
3607 } else { | 3594 } else { |
3608 if (Src0->getType() == IceType_i64) | 3595 if (Src0->getType() == IceType_i64) |
3609 Src0 = loOperand(Src0); | 3596 Src0 = loOperand(Src0); |
3610 Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex); | 3597 Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex); |
3611 // t1 = trunc Src0RF; Dest = t1 | 3598 // t1 = trunc Src0RF; Dest = t1 |
3612 Variable *T = makeReg(Dest->getType()); | 3599 Variable *T = makeReg(Dest->getType()); |
3613 _mov(T, Src0RF); | 3600 _mov(T, Src0RF); |
3614 if (Dest->getType() == IceType_i1) | 3601 if (Dest->getType() == IceType_i1) |
3615 _and(T, T, Ctx->getConstantInt1(1)); | 3602 _and(T, T, Ctx->getConstantInt1(1)); |
3616 _mov(Dest, T); | 3603 _mov(Dest, T); |
3617 } | 3604 } |
3618 break; | 3605 break; |
3619 } | 3606 } |
3620 case InstCast::Fptrunc: | 3607 case InstCast::Fptrunc: |
3621 case InstCast::Fpext: { | 3608 case InstCast::Fpext: { |
3622 // fptrunc: dest.f32 = fptrunc src0.fp64 | 3609 // fptrunc: dest.f32 = fptrunc src0.fp64 |
3623 // fpext: dest.f64 = fptrunc src0.fp32 | 3610 // fpext: dest.f64 = fptrunc src0.fp32 |
3624 const bool IsTrunc = CastKind == InstCast::Fptrunc; | 3611 const bool IsTrunc = CastKind == InstCast::Fptrunc; |
3625 if (isVectorType(Dest->getType())) { | 3612 if (isVectorType(Dest->getType())) { |
3626 Variable *T = makeReg(Dest->getType()); | 3613 UnimplementedLoweringError(this, Inst); |
3627 Context.insert<InstFakeDef>(T, legalizeToReg(Src0)); | |
3628 _mov(Dest, T); | |
3629 UnimplementedError(Func->getContext()->getFlags()); | |
3630 break; | 3614 break; |
3631 } | 3615 } |
3632 assert(Dest->getType() == (IsTrunc ? IceType_f32 : IceType_f64)); | 3616 assert(Dest->getType() == (IsTrunc ? IceType_f32 : IceType_f64)); |
3633 assert(Src0->getType() == (IsTrunc ? IceType_f64 : IceType_f32)); | 3617 assert(Src0->getType() == (IsTrunc ? IceType_f64 : IceType_f32)); |
3634 Variable *Src0R = legalizeToReg(Src0); | 3618 Variable *Src0R = legalizeToReg(Src0); |
3635 Variable *T = makeReg(Dest->getType()); | 3619 Variable *T = makeReg(Dest->getType()); |
3636 _vcvt(T, Src0R, IsTrunc ? InstARM32Vcvt::D2s : InstARM32Vcvt::S2d); | 3620 _vcvt(T, Src0R, IsTrunc ? InstARM32Vcvt::D2s : InstARM32Vcvt::S2d); |
3637 _mov(Dest, T); | 3621 _mov(Dest, T); |
3638 break; | 3622 break; |
3639 } | 3623 } |
3640 case InstCast::Fptosi: | 3624 case InstCast::Fptosi: |
3641 case InstCast::Fptoui: { | 3625 case InstCast::Fptoui: { |
3642 if (isVectorType(Dest->getType())) { | 3626 if (isVectorType(Dest->getType())) { |
3643 Variable *T = makeReg(Dest->getType()); | 3627 UnimplementedLoweringError(this, Inst); |
3644 Context.insert<InstFakeDef>(T, legalizeToReg(Src0)); | |
3645 _mov(Dest, T); | |
3646 UnimplementedError(Func->getContext()->getFlags()); | |
3647 break; | 3628 break; |
3648 } | 3629 } |
3649 | 3630 |
3650 const bool DestIsSigned = CastKind == InstCast::Fptosi; | 3631 const bool DestIsSigned = CastKind == InstCast::Fptosi; |
3651 const bool Src0IsF32 = isFloat32Asserting32Or64(Src0->getType()); | 3632 const bool Src0IsF32 = isFloat32Asserting32Or64(Src0->getType()); |
3652 if (llvm::isa<Variable64On32>(Dest)) { | 3633 if (llvm::isa<Variable64On32>(Dest)) { |
3653 llvm::report_fatal_error("fp-to-i64 should have been pre-lowered."); | 3634 llvm::report_fatal_error("fp-to-i64 should have been pre-lowered."); |
3654 } | 3635 } |
3655 // fptosi: | 3636 // fptosi: |
3656 // t1.fp = vcvt src0.fp | 3637 // t1.fp = vcvt src0.fp |
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3672 Variable *T_1 = makeReg(Dest->getType()); | 3653 Variable *T_1 = makeReg(Dest->getType()); |
3673 lowerCast(InstCast::create(Func, InstCast::Trunc, T_1, T)); | 3654 lowerCast(InstCast::create(Func, InstCast::Trunc, T_1, T)); |
3674 T = T_1; | 3655 T = T_1; |
3675 } | 3656 } |
3676 _mov(Dest, T); | 3657 _mov(Dest, T); |
3677 break; | 3658 break; |
3678 } | 3659 } |
3679 case InstCast::Sitofp: | 3660 case InstCast::Sitofp: |
3680 case InstCast::Uitofp: { | 3661 case InstCast::Uitofp: { |
3681 if (isVectorType(Dest->getType())) { | 3662 if (isVectorType(Dest->getType())) { |
3682 Variable *T = makeReg(Dest->getType()); | 3663 UnimplementedLoweringError(this, Inst); |
3683 Context.insert<InstFakeDef>(T, legalizeToReg(Src0)); | |
3684 _mov(Dest, T); | |
3685 UnimplementedError(Func->getContext()->getFlags()); | |
3686 break; | 3664 break; |
3687 } | 3665 } |
3688 const bool SourceIsSigned = CastKind == InstCast::Sitofp; | 3666 const bool SourceIsSigned = CastKind == InstCast::Sitofp; |
3689 const bool DestIsF32 = isFloat32Asserting32Or64(Dest->getType()); | 3667 const bool DestIsF32 = isFloat32Asserting32Or64(Dest->getType()); |
3690 if (Src0->getType() == IceType_i64) { | 3668 if (Src0->getType() == IceType_i64) { |
3691 llvm::report_fatal_error("i64-to-fp should have been pre-lowered."); | 3669 llvm::report_fatal_error("i64-to-fp should have been pre-lowered."); |
3692 } | 3670 } |
3693 // sitofp: | 3671 // sitofp: |
3694 // t1.i32 = sext src.int @ sign-extends src0 if needed. | 3672 // t1.i32 = sext src.int @ sign-extends src0 if needed. |
3695 // t2.fp32 = vmov t1.i32 | 3673 // t2.fp32 = vmov t1.i32 |
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3724 auto *Assign = InstAssign::create(Func, Dest, Src0); | 3702 auto *Assign = InstAssign::create(Func, Dest, Src0); |
3725 lowerAssign(Assign); | 3703 lowerAssign(Assign); |
3726 return; | 3704 return; |
3727 } | 3705 } |
3728 Type DestType = Dest->getType(); | 3706 Type DestType = Dest->getType(); |
3729 switch (DestType) { | 3707 switch (DestType) { |
3730 case IceType_NUM: | 3708 case IceType_NUM: |
3731 case IceType_void: | 3709 case IceType_void: |
3732 llvm::report_fatal_error("Unexpected bitcast."); | 3710 llvm::report_fatal_error("Unexpected bitcast."); |
3733 case IceType_i1: | 3711 case IceType_i1: |
3734 UnimplementedError(Func->getContext()->getFlags()); | 3712 UnimplementedLoweringError(this, Inst); |
3735 break; | 3713 break; |
3736 case IceType_i8: | 3714 case IceType_i8: |
3737 UnimplementedError(Func->getContext()->getFlags()); | 3715 UnimplementedLoweringError(this, Inst); |
3738 break; | 3716 break; |
3739 case IceType_i16: | 3717 case IceType_i16: |
3740 UnimplementedError(Func->getContext()->getFlags()); | 3718 UnimplementedLoweringError(this, Inst); |
3741 break; | 3719 break; |
3742 case IceType_i32: | 3720 case IceType_i32: |
3743 case IceType_f32: { | 3721 case IceType_f32: { |
3744 Variable *Src0R = legalizeToReg(Src0); | 3722 Variable *Src0R = legalizeToReg(Src0); |
3745 Variable *T = makeReg(DestType); | 3723 Variable *T = makeReg(DestType); |
3746 _mov(T, Src0R); | 3724 _mov(T, Src0R); |
3747 lowerAssign(InstAssign::create(Func, Dest, T)); | 3725 lowerAssign(InstAssign::create(Func, Dest, T)); |
3748 break; | 3726 break; |
3749 } | 3727 } |
3750 case IceType_i64: { | 3728 case IceType_i64: { |
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3777 lowerAssign(InstAssign::create(Func, Dest, T)); | 3755 lowerAssign(InstAssign::create(Func, Dest, T)); |
3778 break; | 3756 break; |
3779 } | 3757 } |
3780 case IceType_v4i1: | 3758 case IceType_v4i1: |
3781 case IceType_v8i1: | 3759 case IceType_v8i1: |
3782 case IceType_v16i1: | 3760 case IceType_v16i1: |
3783 case IceType_v8i16: | 3761 case IceType_v8i16: |
3784 case IceType_v16i8: | 3762 case IceType_v16i8: |
3785 case IceType_v4f32: | 3763 case IceType_v4f32: |
3786 case IceType_v4i32: { | 3764 case IceType_v4i32: { |
3787 // avoid liveness errors | 3765 UnimplementedLoweringError(this, Inst); |
3788 Variable *T = makeReg(DestType); | |
3789 Context.insert<InstFakeDef>(T, legalizeToReg(Src0)); | |
3790 _mov(Dest, T); | |
3791 UnimplementedError(Func->getContext()->getFlags()); | |
3792 break; | 3766 break; |
3793 } | 3767 } |
3794 } | 3768 } |
3795 break; | 3769 break; |
3796 } | 3770 } |
3797 } | 3771 } |
3798 } | 3772 } |
3799 | 3773 |
3800 void TargetARM32::lowerExtractElement(const InstExtractElement *Inst) { | 3774 void TargetARM32::lowerExtractElement(const InstExtractElement *Inst) { |
3801 Variable *Dest = Inst->getDest(); | 3775 UnimplementedLoweringError(this, Inst); |
3802 Type DestType = Dest->getType(); | |
3803 Variable *T = makeReg(DestType); | |
3804 Context.insert<InstFakeDef>(T); | |
3805 _mov(Dest, T); | |
3806 UnimplementedError(Func->getContext()->getFlags()); | |
3807 } | 3776 } |
3808 | 3777 |
3809 namespace { | 3778 namespace { |
3810 // Validates FCMPARM32_TABLE's declaration w.r.t. InstFcmp::FCondition ordering | 3779 // Validates FCMPARM32_TABLE's declaration w.r.t. InstFcmp::FCondition ordering |
3811 // (and naming). | 3780 // (and naming). |
3812 enum { | 3781 enum { |
3813 #define X(val, CC0, CC1) _fcmp_ll_##val, | 3782 #define X(val, CC0, CC1) _fcmp_ll_##val, |
3814 FCMPARM32_TABLE | 3783 FCMPARM32_TABLE |
3815 #undef X | 3784 #undef X |
3816 _fcmp_ll_NUM | 3785 _fcmp_ll_NUM |
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3875 _vmrs(); | 3844 _vmrs(); |
3876 assert(Condition < llvm::array_lengthof(TableFcmp)); | 3845 assert(Condition < llvm::array_lengthof(TableFcmp)); |
3877 return CondWhenTrue(TableFcmp[Condition].CC0, TableFcmp[Condition].CC1); | 3846 return CondWhenTrue(TableFcmp[Condition].CC0, TableFcmp[Condition].CC1); |
3878 } | 3847 } |
3879 } | 3848 } |
3880 } | 3849 } |
3881 | 3850 |
3882 void TargetARM32::lowerFcmp(const InstFcmp *Instr) { | 3851 void TargetARM32::lowerFcmp(const InstFcmp *Instr) { |
3883 Variable *Dest = Instr->getDest(); | 3852 Variable *Dest = Instr->getDest(); |
3884 if (isVectorType(Dest->getType())) { | 3853 if (isVectorType(Dest->getType())) { |
3885 Variable *T = makeReg(Dest->getType()); | 3854 UnimplementedLoweringError(this, Instr); |
3886 Context.insert<InstFakeDef>(T); | |
3887 _mov(Dest, T); | |
3888 UnimplementedError(Func->getContext()->getFlags()); | |
3889 return; | 3855 return; |
3890 } | 3856 } |
3891 | 3857 |
3892 Variable *T = makeReg(IceType_i1); | 3858 Variable *T = makeReg(IceType_i1); |
3893 Operand *_1 = legalize(Ctx->getConstantInt32(1), Legal_Reg | Legal_Flex); | 3859 Operand *_1 = legalize(Ctx->getConstantInt32(1), Legal_Reg | Legal_Flex); |
3894 Operand *_0 = | 3860 Operand *_0 = |
3895 legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex); | 3861 legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex); |
3896 | 3862 |
3897 CondWhenTrue Cond = lowerFcmpCond(Instr); | 3863 CondWhenTrue Cond = lowerFcmpCond(Instr); |
3898 | 3864 |
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4174 return lowerInt32IcmpCond(Condition, Src0, Src1); | 4140 return lowerInt32IcmpCond(Condition, Src0, Src1); |
4175 case IceType_i64: | 4141 case IceType_i64: |
4176 return lowerInt64IcmpCond(Condition, Src0, Src1); | 4142 return lowerInt64IcmpCond(Condition, Src0, Src1); |
4177 } | 4143 } |
4178 } | 4144 } |
4179 | 4145 |
4180 void TargetARM32::lowerIcmp(const InstIcmp *Inst) { | 4146 void TargetARM32::lowerIcmp(const InstIcmp *Inst) { |
4181 Variable *Dest = Inst->getDest(); | 4147 Variable *Dest = Inst->getDest(); |
4182 | 4148 |
4183 if (isVectorType(Dest->getType())) { | 4149 if (isVectorType(Dest->getType())) { |
4184 Variable *T = makeReg(Dest->getType()); | 4150 UnimplementedLoweringError(this, Inst); |
4185 Context.insert<InstFakeDef>(T); | |
4186 _mov(Dest, T); | |
4187 UnimplementedError(Func->getContext()->getFlags()); | |
4188 return; | 4151 return; |
4189 } | 4152 } |
4190 | 4153 |
4191 Operand *_0 = | 4154 Operand *_0 = |
4192 legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex); | 4155 legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex); |
4193 Operand *_1 = legalize(Ctx->getConstantInt32(1), Legal_Reg | Legal_Flex); | 4156 Operand *_1 = legalize(Ctx->getConstantInt32(1), Legal_Reg | Legal_Flex); |
4194 Variable *T = makeReg(IceType_i1); | 4157 Variable *T = makeReg(IceType_i1); |
4195 | 4158 |
4196 _mov(T, _0); | 4159 _mov(T, _0); |
4197 CondWhenTrue Cond = lowerIcmpCond(Inst); | 4160 CondWhenTrue Cond = lowerIcmpCond(Inst); |
4198 _mov_redefined(T, _1, Cond.WhenTrue0); | 4161 _mov_redefined(T, _1, Cond.WhenTrue0); |
4199 _mov(Dest, T); | 4162 _mov(Dest, T); |
4200 | 4163 |
4201 assert(Cond.WhenTrue1 == CondARM32::kNone); | 4164 assert(Cond.WhenTrue1 == CondARM32::kNone); |
4202 | 4165 |
4203 return; | 4166 return; |
4204 } | 4167 } |
4205 | 4168 |
4206 void TargetARM32::lowerInsertElement(const InstInsertElement *Inst) { | 4169 void TargetARM32::lowerInsertElement(const InstInsertElement *Inst) { |
4207 (void)Inst; | 4170 UnimplementedLoweringError(this, Inst); |
4208 UnimplementedError(Func->getContext()->getFlags()); | |
4209 } | 4171 } |
4210 | 4172 |
4211 namespace { | 4173 namespace { |
4212 inline uint64_t getConstantMemoryOrder(Operand *Opnd) { | 4174 inline uint64_t getConstantMemoryOrder(Operand *Opnd) { |
4213 if (auto *Integer = llvm::dyn_cast<ConstantInteger32>(Opnd)) | 4175 if (auto *Integer = llvm::dyn_cast<ConstantInteger32>(Opnd)) |
4214 return Integer->getValue(); | 4176 return Integer->getValue(); |
4215 return Intrinsics::MemoryOrderInvalid; | 4177 return Intrinsics::MemoryOrderInvalid; |
4216 } | 4178 } |
4217 } // end of anonymous namespace | 4179 } // end of anonymous namespace |
4218 | 4180 |
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4742 _rbit(T, ValLoR); | 4704 _rbit(T, ValLoR); |
4743 ValLoR = T; | 4705 ValLoR = T; |
4744 } | 4706 } |
4745 lowerCLZ(Dest, ValLoR, ValHiR); | 4707 lowerCLZ(Dest, ValLoR, ValHiR); |
4746 return; | 4708 return; |
4747 } | 4709 } |
4748 case Intrinsics::Fabs: { | 4710 case Intrinsics::Fabs: { |
4749 Type DestTy = Dest->getType(); | 4711 Type DestTy = Dest->getType(); |
4750 Variable *T = makeReg(DestTy); | 4712 Variable *T = makeReg(DestTy); |
4751 if (isVectorType(DestTy)) { | 4713 if (isVectorType(DestTy)) { |
4752 // Add a fake def to keep liveness consistent in the meantime. | 4714 UnimplementedLoweringError(this, Instr); |
4753 Context.insert<InstFakeDef>(T); | |
4754 _mov(Dest, T); | |
4755 UnimplementedError(Func->getContext()->getFlags()); | |
4756 return; | 4715 return; |
4757 } | 4716 } |
4758 _vabs(T, legalizeToReg(Instr->getArg(0))); | 4717 _vabs(T, legalizeToReg(Instr->getArg(0))); |
4759 _mov(Dest, T); | 4718 _mov(Dest, T); |
4760 return; | 4719 return; |
4761 } | 4720 } |
4762 case Intrinsics::Longjmp: { | 4721 case Intrinsics::Longjmp: { |
4763 llvm::report_fatal_error("longjmp should have been prelowered."); | 4722 llvm::report_fatal_error("longjmp should have been prelowered."); |
4764 } | 4723 } |
4765 case Intrinsics::Memcpy: { | 4724 case Intrinsics::Memcpy: { |
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5336 } | 5295 } |
5337 | 5296 |
5338 void TargetARM32::lowerSelect(const InstSelect *Inst) { | 5297 void TargetARM32::lowerSelect(const InstSelect *Inst) { |
5339 Variable *Dest = Inst->getDest(); | 5298 Variable *Dest = Inst->getDest(); |
5340 Type DestTy = Dest->getType(); | 5299 Type DestTy = Dest->getType(); |
5341 Operand *SrcT = Inst->getTrueOperand(); | 5300 Operand *SrcT = Inst->getTrueOperand(); |
5342 Operand *SrcF = Inst->getFalseOperand(); | 5301 Operand *SrcF = Inst->getFalseOperand(); |
5343 Operand *Condition = Inst->getCondition(); | 5302 Operand *Condition = Inst->getCondition(); |
5344 | 5303 |
5345 if (isVectorType(DestTy)) { | 5304 if (isVectorType(DestTy)) { |
5346 Variable *T = makeReg(DestTy); | 5305 UnimplementedLoweringError(this, Inst); |
5347 Context.insert<InstFakeDef>(T); | |
5348 _mov(Dest, T); | |
5349 UnimplementedError(Func->getContext()->getFlags()); | |
5350 return; | 5306 return; |
5351 } | 5307 } |
5352 | 5308 |
5353 lowerInt1ForSelect(Dest, Condition, legalizeUndef(SrcT), legalizeUndef(SrcF)); | 5309 lowerInt1ForSelect(Dest, Condition, legalizeUndef(SrcT), legalizeUndef(SrcF)); |
5354 } | 5310 } |
5355 | 5311 |
5356 void TargetARM32::lowerStore(const InstStore *Inst) { | 5312 void TargetARM32::lowerStore(const InstStore *Inst) { |
5357 Operand *Value = Inst->getData(); | 5313 Operand *Value = Inst->getData(); |
5358 Operand *Addr = Inst->getAddr(); | 5314 Operand *Addr = Inst->getAddr(); |
5359 OperandARM32Mem *NewAddr = formMemoryOperand(Addr, Value->getType()); | 5315 OperandARM32Mem *NewAddr = formMemoryOperand(Addr, Value->getType()); |
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6496 // However, for compatibility with current NaCl LLVM, don't claim that. | 6452 // However, for compatibility with current NaCl LLVM, don't claim that. |
6497 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; | 6453 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; |
6498 } | 6454 } |
6499 | 6455 |
6500 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM]; | 6456 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM]; |
6501 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; | 6457 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; |
6502 llvm::SmallBitVector TargetARM32::ScratchRegs; | 6458 llvm::SmallBitVector TargetARM32::ScratchRegs; |
6503 | 6459 |
6504 } // end of namespace ARM32 | 6460 } // end of namespace ARM32 |
6505 } // end of namespace Ice | 6461 } // end of namespace Ice |
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