Subzero: Improve the usability of UnimplementedError during lowering.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 2769 matching lines @@
   }
 
   Operand *Src0 = legalizeUndef(Instr->getSrc(0));
   Operand *Src1 = legalizeUndef(Instr->getSrc(1));
   if (DestTy == IceType_i64) {
     lowerInt64Arithmetic(Instr->getOp(), Instr->getDest(), Src0, Src1);
     return;
   }
 
   if (isVectorType(DestTy)) {
-    // Add a fake def to keep liveness consistent in the meantime.
-    Variable *T = makeReg(DestTy);
-    Context.insert<InstFakeDef>(T);
-    _mov(Dest, T);
-    UnimplementedError(Func->getContext()->getFlags());
+    UnimplementedLoweringError(this, Instr);
     return;
   }
 
   // DestTy is a non-i64 scalar.
   Variable *T = makeReg(DestTy);
 
   // * Handle div/rem separately. They require a non-legalized Src1 to inspect
   // whether or not Src1 is a non-zero constant. Once legalized it is more
   // difficult to determine (constant may be moved to a register).
   // * Handle floating point arithmetic separately: they require Src1 to be
@@ skipping 684 matching lines @@
 void TargetARM32::lowerCast(const InstCast *Inst) {
   InstCast::OpKind CastKind = Inst->getCastKind();
   Variable *Dest = Inst->getDest();
   Operand *Src0 = legalizeUndef(Inst->getSrc(0));
   switch (CastKind) {
   default:
     Func->setError("Cast type not supported");
     return;
   case InstCast::Sext: {
     if (isVectorType(Dest->getType())) {
-      Variable *T = makeReg(Dest->getType());
-      Context.insert<InstFakeDef>(T, legalizeToReg(Src0));
-      _mov(Dest, T);
-      UnimplementedError(Func->getContext()->getFlags());
+      UnimplementedLoweringError(this, Inst);
     } else if (Dest->getType() == IceType_i64) {
       // t1=sxtb src; t2= mov t1 asr #31; dst.lo=t1; dst.hi=t2
       Constant *ShiftAmt = Ctx->getConstantInt32(31);
       auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
       auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *T_Lo = makeReg(DestLo->getType());
       if (Src0->getType() == IceType_i32) {
         Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
         _mov(T_Lo, Src0RF);
       } else if (Src0->getType() != IceType_i1) {
@@ skipping 24 matching lines @@
       Constant *_0 = Ctx->getConstantZero(IceType_i32);
       Operand *_m1 = Ctx->getConstantInt(Dest->getType(), -1);
       Variable *T = makeReg(Dest->getType());
       lowerInt1ForSelect(T, Src0, _m1, _0);
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Zext: {
     if (isVectorType(Dest->getType())) {
-      Variable *T = makeReg(Dest->getType());
-      Context.insert<InstFakeDef>(T, legalizeToReg(Src0));
-      _mov(Dest, T);
-      UnimplementedError(Func->getContext()->getFlags());
+      UnimplementedLoweringError(this, Inst);
     } else if (Dest->getType() == IceType_i64) {
       // t1=uxtb src; dst.lo=t1; dst.hi=0
       Operand *_0 =
           legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
       auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
       auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *T_Lo = makeReg(DestLo->getType());
 
       switch (Src0->getType()) {
       default: {
@@ skipping 32 matching lines @@
       // t1 = uxt src; dst = t1
       Variable *Src0R = legalizeToReg(Src0);
       Variable *T = makeReg(Dest->getType());
       _uxt(T, Src0R);
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Trunc: {
     if (isVectorType(Dest->getType())) {
-      Variable *T = makeReg(Dest->getType());
-      Context.insert<InstFakeDef>(T, legalizeToReg(Src0));
-      _mov(Dest, T);
-      UnimplementedError(Func->getContext()->getFlags());
+      UnimplementedLoweringError(this, Inst);
     } else {
       if (Src0->getType() == IceType_i64)
         Src0 = loOperand(Src0);
       Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
       // t1 = trunc Src0RF; Dest = t1
       Variable *T = makeReg(Dest->getType());
       _mov(T, Src0RF);
       if (Dest->getType() == IceType_i1)
         _and(T, T, Ctx->getConstantInt1(1));
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Fptrunc:
   case InstCast::Fpext: {
     // fptrunc: dest.f32 = fptrunc src0.fp64
     // fpext: dest.f64 = fptrunc src0.fp32
     const bool IsTrunc = CastKind == InstCast::Fptrunc;
     if (isVectorType(Dest->getType())) {
-      Variable *T = makeReg(Dest->getType());
-      Context.insert<InstFakeDef>(T, legalizeToReg(Src0));
-      _mov(Dest, T);
-      UnimplementedError(Func->getContext()->getFlags());
+      UnimplementedLoweringError(this, Inst);
       break;
     }
     assert(Dest->getType() == (IsTrunc ? IceType_f32 : IceType_f64));
     assert(Src0->getType() == (IsTrunc ? IceType_f64 : IceType_f32));
     Variable *Src0R = legalizeToReg(Src0);
     Variable *T = makeReg(Dest->getType());
     _vcvt(T, Src0R, IsTrunc ? InstARM32Vcvt::D2s : InstARM32Vcvt::S2d);
     _mov(Dest, T);
     break;
   }
   case InstCast::Fptosi:
   case InstCast::Fptoui: {
     if (isVectorType(Dest->getType())) {
-      Variable *T = makeReg(Dest->getType());
-      Context.insert<InstFakeDef>(T, legalizeToReg(Src0));
-      _mov(Dest, T);
-      UnimplementedError(Func->getContext()->getFlags());
+      UnimplementedLoweringError(this, Inst);
       break;
     }
 
     const bool DestIsSigned = CastKind == InstCast::Fptosi;
     const bool Src0IsF32 = isFloat32Asserting32Or64(Src0->getType());
     if (llvm::isa<Variable64On32>(Dest)) {
       llvm::report_fatal_error("fp-to-i64 should have been pre-lowered.");
     }
     // fptosi:
     //     t1.fp = vcvt src0.fp
@@ skipping 15 matching lines @@
       Variable *T_1 = makeReg(Dest->getType());
       lowerCast(InstCast::create(Func, InstCast::Trunc, T_1, T));
       T = T_1;
     }
     _mov(Dest, T);
     break;
   }
   case InstCast::Sitofp:
   case InstCast::Uitofp: {
     if (isVectorType(Dest->getType())) {
-      Variable *T = makeReg(Dest->getType());
-      Context.insert<InstFakeDef>(T, legalizeToReg(Src0));
-      _mov(Dest, T);
-      UnimplementedError(Func->getContext()->getFlags());
+      UnimplementedLoweringError(this, Inst);
       break;
     }
     const bool SourceIsSigned = CastKind == InstCast::Sitofp;
     const bool DestIsF32 = isFloat32Asserting32Or64(Dest->getType());
     if (Src0->getType() == IceType_i64) {
       llvm::report_fatal_error("i64-to-fp should have been pre-lowered.");
     }
     // sitofp:
     //     t1.i32 = sext src.int    @ sign-extends src0 if needed.
     //     t2.fp32 = vmov t1.i32
@@ skipping 28 matching lines @@
       auto *Assign = InstAssign::create(Func, Dest, Src0);
       lowerAssign(Assign);
       return;
     }
     Type DestType = Dest->getType();
     switch (DestType) {
     case IceType_NUM:
     case IceType_void:
       llvm::report_fatal_error("Unexpected bitcast.");
     case IceType_i1:
-      UnimplementedError(Func->getContext()->getFlags());
+      UnimplementedLoweringError(this, Inst);
       break;
     case IceType_i8:
-      UnimplementedError(Func->getContext()->getFlags());
+      UnimplementedLoweringError(this, Inst);
       break;
     case IceType_i16:
-      UnimplementedError(Func->getContext()->getFlags());
+      UnimplementedLoweringError(this, Inst);
       break;
     case IceType_i32:
     case IceType_f32: {
       Variable *Src0R = legalizeToReg(Src0);
       Variable *T = makeReg(DestType);
       _mov(T, Src0R);
       lowerAssign(InstAssign::create(Func, Dest, T));
       break;
     }
     case IceType_i64: {
@@ skipping 26 matching lines @@
       lowerAssign(InstAssign::create(Func, Dest, T));
       break;
     }
     case IceType_v4i1:
     case IceType_v8i1:
     case IceType_v16i1:
     case IceType_v8i16:
     case IceType_v16i8:
     case IceType_v4f32:
     case IceType_v4i32: {
-      // avoid liveness errors
-      Variable *T = makeReg(DestType);
-      Context.insert<InstFakeDef>(T, legalizeToReg(Src0));
-      _mov(Dest, T);
-      UnimplementedError(Func->getContext()->getFlags());
+      UnimplementedLoweringError(this, Inst);
       break;
     }
     }
     break;
   }
   }
 }
 
 void TargetARM32::lowerExtractElement(const InstExtractElement *Inst) {
-  Variable *Dest = Inst->getDest();
-  Type DestType = Dest->getType();
-  Variable *T = makeReg(DestType);
-  Context.insert<InstFakeDef>(T);
-  _mov(Dest, T);
-  UnimplementedError(Func->getContext()->getFlags());
+  UnimplementedLoweringError(this, Inst);
 }
 
 namespace {
 // Validates FCMPARM32_TABLE's declaration w.r.t. InstFcmp::FCondition ordering
 // (and naming).
 enum {
 #define X(val, CC0, CC1) _fcmp_ll_##val,
   FCMPARM32_TABLE
 #undef X
       _fcmp_ll_NUM
@@ skipping 58 matching lines @@
     _vmrs();
     assert(Condition < llvm::array_lengthof(TableFcmp));
     return CondWhenTrue(TableFcmp[Condition].CC0, TableFcmp[Condition].CC1);
   }
   }
 }
 
 void TargetARM32::lowerFcmp(const InstFcmp *Instr) {
   Variable *Dest = Instr->getDest();
   if (isVectorType(Dest->getType())) {
-    Variable *T = makeReg(Dest->getType());
-    Context.insert<InstFakeDef>(T);
-    _mov(Dest, T);
-    UnimplementedError(Func->getContext()->getFlags());
+    UnimplementedLoweringError(this, Instr);
     return;
   }
 
   Variable *T = makeReg(IceType_i1);
   Operand *_1 = legalize(Ctx->getConstantInt32(1), Legal_Reg | Legal_Flex);
   Operand *_0 =
       legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
 
   CondWhenTrue Cond = lowerFcmpCond(Instr);
 
@@ skipping 275 matching lines @@
     return lowerInt32IcmpCond(Condition, Src0, Src1);
   case IceType_i64:
     return lowerInt64IcmpCond(Condition, Src0, Src1);
   }
 }
 
 void TargetARM32::lowerIcmp(const InstIcmp *Inst) {
   Variable *Dest = Inst->getDest();
 
   if (isVectorType(Dest->getType())) {
-    Variable *T = makeReg(Dest->getType());
-    Context.insert<InstFakeDef>(T);
-    _mov(Dest, T);
-    UnimplementedError(Func->getContext()->getFlags());
+    UnimplementedLoweringError(this, Inst);
     return;
   }
 
   Operand *_0 =
       legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
   Operand *_1 = legalize(Ctx->getConstantInt32(1), Legal_Reg | Legal_Flex);
   Variable *T = makeReg(IceType_i1);
 
   _mov(T, _0);
   CondWhenTrue Cond = lowerIcmpCond(Inst);
   _mov_redefined(T, _1, Cond.WhenTrue0);
   _mov(Dest, T);
 
   assert(Cond.WhenTrue1 == CondARM32::kNone);
 
   return;
 }
 
 void TargetARM32::lowerInsertElement(const InstInsertElement *Inst) {
-  (void)Inst;
-  UnimplementedError(Func->getContext()->getFlags());
+  UnimplementedLoweringError(this, Inst);
 }
 
 namespace {
 inline uint64_t getConstantMemoryOrder(Operand *Opnd) {
   if (auto *Integer = llvm::dyn_cast<ConstantInteger32>(Opnd))
     return Integer->getValue();
   return Intrinsics::MemoryOrderInvalid;
 }
 } // end of anonymous namespace
 
@@ skipping 523 matching lines @@
       _rbit(T, ValLoR);
       ValLoR = T;
     }
     lowerCLZ(Dest, ValLoR, ValHiR);
     return;
   }
   case Intrinsics::Fabs: {
     Type DestTy = Dest->getType();
     Variable *T = makeReg(DestTy);
     if (isVectorType(DestTy)) {
-      // Add a fake def to keep liveness consistent in the meantime.
-      Context.insert<InstFakeDef>(T);
-      _mov(Dest, T);
-      UnimplementedError(Func->getContext()->getFlags());
+      UnimplementedLoweringError(this, Instr);
       return;
     }
     _vabs(T, legalizeToReg(Instr->getArg(0)));
     _mov(Dest, T);
     return;
   }
   case Intrinsics::Longjmp: {
     llvm::report_fatal_error("longjmp should have been prelowered.");
   }
   case Intrinsics::Memcpy: {
@@ skipping 570 matching lines @@
 }
 
 void TargetARM32::lowerSelect(const InstSelect *Inst) {
   Variable *Dest = Inst->getDest();
   Type DestTy = Dest->getType();
   Operand *SrcT = Inst->getTrueOperand();
   Operand *SrcF = Inst->getFalseOperand();
   Operand *Condition = Inst->getCondition();
 
   if (isVectorType(DestTy)) {
-    Variable *T = makeReg(DestTy);
-    Context.insert<InstFakeDef>(T);
-    _mov(Dest, T);
-    UnimplementedError(Func->getContext()->getFlags());
+    UnimplementedLoweringError(this, Inst);
     return;
   }
 
   lowerInt1ForSelect(Dest, Condition, legalizeUndef(SrcT), legalizeUndef(SrcF));
 }
 
 void TargetARM32::lowerStore(const InstStore *Inst) {
   Operand *Value = Inst->getData();
   Operand *Addr = Inst->getAddr();
   OperandARM32Mem *NewAddr = formMemoryOperand(Addr, Value->getType());
@@ skipping 1136 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 llvm::SmallBitVector TargetARM32::ScratchRegs;
 
 } // end of namespace ARM32
 } // end of namespace Ice