MIPS: Add FPXX support to MIPS32R2

src/mips/assembler-mips.cc

Index: src/mips/assembler-mips.cc
diff --git a/src/mips/assembler-mips.cc b/src/mips/assembler-mips.cc
index a8b6cc7c32dc9d15a9e2f0e054bdc34f9d9bc32c..192fe484f6968c9689a8728933bb9f2e21d103c8 100644
--- a/src/mips/assembler-mips.cc
+++ b/src/mips/assembler-mips.cc
@@ -2105,7 +2105,7 @@ void Assembler::ldc1(FPURegister fd, const MemOperand& src) {
       GenInstrImmediate(LW, at, at, Register::kExponentOffset);
       mthc1(at, fd);
     }
-  } else {  // fp32 mode.
+  } else if (IsFp32Mode()) {  // fp32 mode.
     if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
       GenInstrImmediate(LWC1, src.rm(), fd,
                         src.offset_ + Register::kMantissaOffset);
@@ -2120,6 +2120,22 @@ void Assembler::ldc1(FPURegister fd, const MemOperand& src) {
       nextfpreg.setcode(fd.code() + 1);
       GenInstrImmediate(LWC1, at, nextfpreg, Register::kExponentOffset);
     }
+  } else {
+    DCHECK(IsFpxxMode());
+    // Currently we support FPXX on Mips32r2 and Mips32r6
+    DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
+    if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
+      GenInstrImmediate(LWC1, src.rm(), fd,
+                        src.offset_ + Register::kMantissaOffset);
+      GenInstrImmediate(LW, src.rm(), at,
+                        src.offset_ + Register::kExponentOffset);
+      mthc1(at, fd);

[balazs.kilvady, 2016/01/27 11:50:08]

Why we use GenInstrImmediate() for LW and LWC1 if mthc1() can be called? Coud
not we use lw(); lwc1() everywhere in this function? Otherwise the code is fine.

[ivica.bogosavljevic, 2016/01/27 12:49:34]

Good point. I just copied the above code. I will remove GenInstrImmediate in
both ldc1 and sdc1.

On 2016/01/27 11:50:08, balazs.kilvady wrote:

+    } else {  // Offset > 16 bits, use multiple instructions to load.
+      LoadRegPlusOffsetToAt(src);
+      GenInstrImmediate(LWC1, at, fd, Register::kMantissaOffset);
+      GenInstrImmediate(LW, at, at, Register::kExponentOffset);
+      mthc1(at, fd);
+    }
   }
 }
 
@@ -2152,7 +2168,7 @@ void Assembler::sdc1(FPURegister fd, const MemOperand& src) {
       mfhc1(t8, fd);
       GenInstrImmediate(SW, at, t8, Register::kExponentOffset);
     }
-  } else {  // fp32 mode.
+  } else if (IsFp32Mode()) {  // fp32 mode.
     if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
       GenInstrImmediate(SWC1, src.rm(), fd,
                         src.offset_ + Register::kMantissaOffset);
@@ -2167,6 +2183,22 @@ void Assembler::sdc1(FPURegister fd, const MemOperand& src) {
       nextfpreg.setcode(fd.code() + 1);
       GenInstrImmediate(SWC1, at, nextfpreg, Register::kExponentOffset);
     }
+  } else {
+    DCHECK(IsFpxxMode());
+    // Currently we support FPXX on Mips32r2 and Mips32r6
+    DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
+    if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
+      GenInstrImmediate(SWC1, src.rm(), fd,
+                        src.offset_ + Register::kMantissaOffset);
+      mfhc1(at, fd);
+      GenInstrImmediate(SW, src.rm(), at,
+                        src.offset_ + Register::kExponentOffset);
+    } else {  // Offset > 16 bits, use multiple instructions to load.
+      LoadRegPlusOffsetToAt(src);
+      GenInstrImmediate(SWC1, at, fd, Register::kMantissaOffset);
+      mfhc1(t8, fd);
+      GenInstrImmediate(SW, at, t8, Register::kExponentOffset);
+    }
   }
 }