MIPS: Add FPXX support to MIPS32R2

MIPS: Add FPXX support to MIPS32R2

The JIT code generated by V8 is FPXX compliant
when v8 compiled with FPXX flag. This allows the code to
run in both FP=1 and FP=0 mode. It also alows v8 to be used
as a library by both FP32 and FP64 binaries.

BUG=

Committed: https://crrev.com/95110dde666158a230a823fd50a68558ad772320
Cr-Commit-Position: refs/heads/master@{#33576}

[ivica.bogosavljevic, 2016-01-15 16:16:14]

ivica.bogosavljevic@imgtec.com changed reviewers:
+ akos.palfi@imgtec.com, gergely.kis@imgtec.com, ilija.pavlovic@imgtec.com,
marija.antic@imgtec.com, miran.karic@imgtec.com, paul.lind@imgtec.com

[ivica.bogosavljevic, 2016-01-15 16:16:14]

Hi guys!

This is the initial proposal of FPXX on MIPS32R2. The fix is quite simple, so it
shouldn't be a problem to understand.

The octane suite is now fixed. I am running all the other tests, but since they
are running on the board, it's taken some time. Also, it's possible that I will
find bugs in tests or code and post fixes in the upcoming patchsets.

Ivica

[ivica.bogosavljevic, 2016-01-20 09:11:44]

PTAL

[Ilija.Pavlovic1, 2016-01-26 13:18:07]

ilija.pavlovic@imgtec.com changed reviewers:
+ Ilija.Pavlovic@imgtec.com

[Ilija.Pavlovic1, 2016-01-26 13:18:07]

These adaptations seems to me OK.

[balazs.kilvady, 2016-01-27 11:50:08]

balazs.kilvady@imgtec.com changed reviewers:
+ balazs.kilvady@imgtec.com
- Ilija.Pavlovic@imgtec.com

[balazs.kilvady, 2016-01-27 11:50:09]

lgtm with a questions: in the review and have you run tests on a board?

https://codereview.chromium.org/1586223004/diff/20001/src/mips/assembler-mips.cc
File src/mips/assembler-mips.cc (right):

https://codereview.chromium.org/1586223004/diff/20001/src/mips/assembler-mips...
src/mips/assembler-mips.cc:2132: mthc1(at, fd);
Why we use GenInstrImmediate() for LW and LWC1 if mthc1() can be called? Coud
not we use lw(); lwc1() everywhere in this function? Otherwise the code is fine.

[balazs.kilvady, 2016-01-27 12:16:49]

Also please improve the message if you want to land it :)

[ivica.bogosavljevic, 2016-01-27 12:40:38]

Description was changed from

==========
MIPS: Initial draft of FPXX for MIPS32R2

BUG=
==========

to

==========
MIPS: Add FPXX support to MIPS32R2

The JIT code generated by V8 is FPXX compliant
when v8 compiled with FPXX flag. This allows the code to
run in both FP=1 and FP=0 mode. It also alows v8 to be used
as a library by both FP32 and FP64 binaries.

BUG=
==========

[ivica.bogosavljevic, 2016-01-27 12:49:28]

On 2016/01/27 11:50:09, balazs.kilvady wrote:
> lgtm with a questions: in the review and have you run tests on a board?
> 
>
https://codereview.chromium.org/1586223004/diff/20001/src/mips/assembler-mips.cc
> File src/mips/assembler-mips.cc (right):
> 
>
https://codereview.chromium.org/1586223004/diff/20001/src/mips/assembler-mips...
> src/mips/assembler-mips.cc:2132: mthc1(at, fd);
> Why we use GenInstrImmediate() for LW and LWC1 if mthc1() can be called? Coud
> not we use lw(); lwc1() everywhere in this function? Otherwise the code is
fine.

I ran the tests on the board and they are passing. Since this is FPXX binary,
the kernel will start it in either FP32 or FP64 mode, depending on kernel
configuration. We need to set-up testing environment since FPXX can be run 
both way, this is covered here:
https://github.com/paul99/v8m-rb/issues/239

[ivica.bogosavljevic, 2016-01-27 12:49:35]

https://codereview.chromium.org/1586223004/diff/20001/src/mips/assembler-mips.cc
File src/mips/assembler-mips.cc (right):

https://codereview.chromium.org/1586223004/diff/20001/src/mips/assembler-mips...
src/mips/assembler-mips.cc:2132: mthc1(at, fd);
Good point. I just copied the above code. I will remove GenInstrImmediate in
both ldc1 and sdc1.

On 2016/01/27 11:50:08, balazs.kilvady wrote:
> Why we use GenInstrImmediate() for LW and LWC1 if mthc1() can be called? Coud
> not we use lw(); lwc1() everywhere in this function? Otherwise the code is
fine.

[ivica.bogosavljevic, 2016-01-27 13:22:48]

The CQ bit was checked by ivica.bogosavljevic@imgtec.com to run a CQ dry run

[commit-bot: I haz the power, 2016-01-27 13:22:56]

Dry run: CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1586223004/40001
View timeline at
 https://chromium-cq-status.appspot.com/patch-timeline/1586223004/40001

[commit-bot: I haz the power, 2016-01-27 13:48:41]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2016-01-27 13:48:42]

Dry run: This issue passed the CQ dry run.

[ivica.bogosavljevic, 2016-01-28 09:30:17]

The CQ bit was checked by ivica.bogosavljevic@imgtec.com

[ivica.bogosavljevic, 2016-01-28 09:30:17]

The patchset sent to the CQ was uploaded after l-g-t-m from
balazs.kilvady@imgtec.com
Link to the patchset: https://codereview.chromium.org/1586223004/#ps40001
(title: "Rebasing changes from master")

[commit-bot: I haz the power, 2016-01-28 09:30:23]

CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1586223004/40001
View timeline at
 https://chromium-cq-status.appspot.com/patch-timeline/1586223004/40001

[commit-bot: I haz the power, 2016-01-28 09:33:53]

Description was changed from

==========
MIPS: Add FPXX support to MIPS32R2

The JIT code generated by V8 is FPXX compliant
when v8 compiled with FPXX flag. This allows the code to
run in both FP=1 and FP=0 mode. It also alows v8 to be used
as a library by both FP32 and FP64 binaries.

BUG=
==========

to

==========
MIPS: Add FPXX support to MIPS32R2

The JIT code generated by V8 is FPXX compliant
when v8 compiled with FPXX flag. This allows the code to
run in both FP=1 and FP=0 mode. It also alows v8 to be used
as a library by both FP32 and FP64 binaries.

BUG=
==========

[commit-bot: I haz the power, 2016-01-28 09:33:55]

Committed patchset #3 (id:40001)

[commit-bot: I haz the power, 2016-01-28 09:34:04]

Description was changed from

==========
MIPS: Add FPXX support to MIPS32R2

The JIT code generated by V8 is FPXX compliant
when v8 compiled with FPXX flag. This allows the code to
run in both FP=1 and FP=0 mode. It also alows v8 to be used
as a library by both FP32 and FP64 binaries.

BUG=
==========

to

==========
MIPS: Add FPXX support to MIPS32R2

The JIT code generated by V8 is FPXX compliant
when v8 compiled with FPXX flag. This allows the code to
run in both FP=1 and FP=0 mode. It also alows v8 to be used
as a library by both FP32 and FP64 binaries.

BUG=

Committed: https://crrev.com/95110dde666158a230a823fd50a68558ad772320
Cr-Commit-Position: refs/heads/master@{#33576}
==========

[commit-bot: I haz the power, 2016-01-28 09:34:05]

Patchset 3 (id:??) landed as
https://crrev.com/95110dde666158a230a823fd50a68558ad772320
Cr-Commit-Position: refs/heads/master@{#33576}

[ivica.bogosavljevic, 2016-01-28 11:53:33]

A revert of this CL (patchset #3 id:40001) has been created in
https://codereview.chromium.org/1646813003/ by ivica.bogosavljevic@imgtec.com.

The reason for reverting is: Revert patch due to a number of failures appearing
on the MIPS v8 simulator.

[Paul Lind, 2016-02-01 04:27:36]

plind44@gmail.com changed reviewers:
+ plind44@gmail.com

[Paul Lind, 2016-02-01 04:27:36]

One drive-by-comment, but don't know the source of the problem with this CL.

https://codereview.chromium.org/1586223004/diff/40001/src/mips/assembler-mips.cc
File src/mips/assembler-mips.cc (right):

https://codereview.chromium.org/1586223004/diff/40001/src/mips/assembler-mips...
src/mips/assembler-mips.cc:2117: } else {
As far as I can see this block is same as fp64 case. Suggest starting with if
(IsFp32Mode()), and then let fp64, and ffpxx land under a single else, to avoid
code duplication. (with appropriate DCHECKs, etc)