Subzero. RAII NaCl Bundling.

src/IceTargetLoweringX8664.cpp

 //===- subzero/src/IceTargetLoweringX8664.cpp - x86-64 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 147 matching lines @@
   // add Adjustment, %esp
   // %rsp = fake-def %esp
   // add %r15, %rsp
   // .bundle_end
   //
   // The fake-defs ensure that the
   //
   // add Adjustment, %esp
   //
   // instruction is not DCE'd.
-  _bundle_lock();
+  AutoBundle _(this);
   _redefined(Context.insert<InstFakeDef>(esp, rsp));
   _add(esp, Adjustment);
   _redefined(Context.insert<InstFakeDef>(rsp, esp));
   _add(rsp, r15);
-  _bundle_unlock();
 }
 
 void TargetX8664::_mov_sp(Operand *NewValue) {
   assert(NewValue->getType() == IceType_i32);
 
   Variable *esp = getPhysicalRegister(Traits::RegisterSet::Reg_esp);
   Variable *rsp =
       getPhysicalRegister(Traits::RegisterSet::Reg_rsp, IceType_i64);
 
-  if (NeedSandboxing) {
-    _bundle_lock();
-  }
+  AutoBundle _(this);
 
   _redefined(Context.insert<InstFakeDef>(esp, rsp));
   _redefined(_mov(esp, NewValue));
   _redefined(Context.insert<InstFakeDef>(rsp, esp));
 
   if (!NeedSandboxing) {
     return;
   }
 
   Variable *r15 =
       getPhysicalRegister(Traits::RegisterSet::Reg_r15, IceType_i64);
   _add(rsp, r15);
-  _bundle_unlock();
 }
 
 void TargetX8664::_push_rbp() {
   assert(NeedSandboxing);
 
   Constant *_0 = Ctx->getConstantZero(IceType_i32);
   Variable *ebp =
       getPhysicalRegister(Traits::RegisterSet::Reg_ebp, IceType_i32);
   Variable *rsp =
       getPhysicalRegister(Traits::RegisterSet::Reg_rsp, IceType_i64);
   auto *TopOfStack = llvm::cast<X86OperandMem>(
       legalize(X86OperandMem::create(Func, IceType_i32, rsp, _0),
                Legal_Reg | Legal_Mem));
 
   // Emits a sequence:
   //
   //   .bundle_start
   //   push 0
   //   mov %ebp, %(rsp)
   //   .bundle_end
   //
   // to avoid leaking the upper 32-bits (i.e., the sandbox address.)
-  _bundle_lock();
+  AutoBundle _(this);
   _push(_0);
   Context.insert<typename Traits::Insts::Store>(ebp, TopOfStack);
-  _bundle_unlock();
 }
 
 Traits::X86OperandMem *TargetX8664::_sandbox_mem_reference(X86OperandMem *Mem) {
   // In x86_64-nacl, all memory references are relative to %r15 (i.e., %rzp.)
   // NaCl sandboxing also requires that any registers that are not %rsp and
   // %rbp to be 'truncated' to 32-bit before memory access.
   assert(NeedSandboxing);
   Variable *Base = Mem->getBase();
   Variable *Index = Mem->getIndex();
   uint16_t Shift = 0;
@@ skipping 108 matching lines @@
 
   Variable *esp =
       getPhysicalRegister(Traits::RegisterSet::Reg_esp, IceType_i32);
   Variable *r15 =
       getPhysicalRegister(Traits::RegisterSet::Reg_r15, IceType_i64);
 
   // .bundle_start
   // sub Adjustment, %esp
   // add %r15, %rsp
   // .bundle_end
-  _bundle_lock();
+  AutoBundle _(this);
   _redefined(Context.insert<InstFakeDef>(esp, rsp));
   _sub(esp, Adjustment);
   _redefined(Context.insert<InstFakeDef>(rsp, esp));
   _add(rsp, r15);
-  _bundle_unlock();
 }
 
 void TargetX8664::initSandbox() {
   assert(NeedSandboxing);
   Context.init(Func->getEntryNode());
   Context.setInsertPoint(Context.getCur());
   Variable *r15 =
       getPhysicalRegister(Traits::RegisterSet::Reg_r15, IceType_i64);
   Context.insert<InstFakeDef>(r15);
   Context.insert<InstFakeUse>(r15);
 }
 
 void TargetX8664::lowerIndirectJump(Variable *JumpTarget) {
+  std::unique_ptr<AutoBundle> Bundler;
+
   if (!NeedSandboxing) {
     Variable *T = makeReg(IceType_i64);
     _movzx(T, JumpTarget);
     JumpTarget = T;
   } else {
     Variable *T = makeReg(IceType_i32);
     Variable *T64 = makeReg(IceType_i64);
     Variable *r15 =
         getPhysicalRegister(Traits::RegisterSet::Reg_r15, IceType_i64);
 
     _mov(T, JumpTarget);
-    _bundle_lock();
+    Bundler = makeUnique<AutoBundle>(this);
     const SizeT BundleSize =
         1 << Func->getAssembler<>()->getBundleAlignLog2Bytes();
     _and(T, Ctx->getConstantInt32(~(BundleSize - 1)));
     _movzx(T64, T);
     _add(T64, r15);
     JumpTarget = T64;
   }
 
   _jmp(JumpTarget);
-  if (NeedSandboxing)
-    _bundle_unlock();
 }
 
 namespace {
 static inline TargetX8664::Traits::RegisterSet::AllRegisters
 getRegisterForXmmArgNum(uint32_t ArgNum) {
   assert(ArgNum < TargetX8664::Traits::X86_MAX_XMM_ARGS);
   return static_cast<TargetX8664::Traits::RegisterSet::AllRegisters>(
       TargetX8664::Traits::RegisterSet::Reg_xmm0 + ArgNum);
 }
 
@@ skipping 187 matching lines @@
       // emitted call needs a i64 register (for textual asm.)
       Variable *T = makeReg(IceType_i64);
       _movzx(T, CallTargetR);
       CallTarget = T;
     }
     NewCall = Context.insert<Traits::Insts::Call>(ReturnReg, CallTarget);
   } else {
     ReturnAddress = InstX86Label::create(Func, this);
     ReturnAddress->setIsReturnLocation(true);
     constexpr bool SuppressMangling = true;
-    if (CallTargetR == nullptr) {
-      _bundle_lock(InstBundleLock::Opt_PadToEnd);
-      _push(Ctx->getConstantSym(0, ReturnAddress->getName(Func),
-                                SuppressMangling));
-    } else {
-      Variable *T = makeReg(IceType_i32);
-      Variable *T64 = makeReg(IceType_i64);
-      Variable *r15 =
-          getPhysicalRegister(Traits::RegisterSet::Reg_r15, IceType_i64);
+    /* AutoBundle scoping */ {
+      std::unique_ptr<AutoBundle> Bundler;
+      if (CallTargetR == nullptr) {
+        Bundler = makeUnique<AutoBundle>(this, InstBundleLock::Opt_PadToEnd);
+        _push(Ctx->getConstantSym(0, ReturnAddress->getName(Func),
+                                  SuppressMangling));
+      } else {
+        Variable *T = makeReg(IceType_i32);
+        Variable *T64 = makeReg(IceType_i64);
+        Variable *r15 =
+            getPhysicalRegister(Traits::RegisterSet::Reg_r15, IceType_i64);
 
-      _mov(T, CallTargetR);
-      _bundle_lock(InstBundleLock::Opt_PadToEnd);
-      _push(Ctx->getConstantSym(0, ReturnAddress->getName(Func),
-                                SuppressMangling));
-      const SizeT BundleSize =
-          1 << Func->getAssembler<>()->getBundleAlignLog2Bytes();
-      _and(T, Ctx->getConstantInt32(~(BundleSize - 1)));
-      _movzx(T64, T);
-      _add(T64, r15);
-      CallTarget = T64;
+        _mov(T, CallTargetR);
+        Bundler = makeUnique<AutoBundle>(this, InstBundleLock::Opt_PadToEnd);
+        _push(Ctx->getConstantSym(0, ReturnAddress->getName(Func),
+                                  SuppressMangling));
+        const SizeT BundleSize =
+            1 << Func->getAssembler<>()->getBundleAlignLog2Bytes();
+        _and(T, Ctx->getConstantInt32(~(BundleSize - 1)));
+        _movzx(T64, T);
+        _add(T64, r15);
+        CallTarget = T64;
+      }
+
+      NewCall = Context.insert<Traits::Insts::Jmp>(CallTarget);
     }
-
-    NewCall = Context.insert<Traits::Insts::Jmp>(CallTarget);
-    _bundle_unlock();
     if (ReturnReg != nullptr) {
       Context.insert<InstFakeDef>(ReturnReg);
     }
 
     Context.insert(ReturnAddress);
   }
 
   // Insert a register-kill pseudo instruction.
   Context.insert<InstFakeKill>(NewCall);
 
@@ skipping 215 matching lines @@
         getPhysicalRegister(Traits::RegisterSet::Reg_esp, IceType_i32);
     Variable *r15 =
         getPhysicalRegister(Traits::RegisterSet::Reg_r15, IceType_i64);
 
     if (!NeedSandboxing) {
       _push(rbp);
       _mov(rbp, rsp);
     } else {
       _push_rbp();
 
-      _bundle_lock();
+      AutoBundle _(this);
       _redefined(Context.insert<InstFakeDef>(ebp, rbp));
       _redefined(Context.insert<InstFakeDef>(esp, rsp));
       _mov(ebp, esp);
       _redefined(Context.insert<InstFakeDef>(rsp, esp));
       _add(rbp, r15);
-      _bundle_unlock();
     }
     // Keep ebp live for late-stage liveness analysis (e.g. asm-verbose mode).
     Context.insert<InstFakeUse>(rbp);
   }
 
   // Align the variables area. SpillAreaPaddingBytes is the size of the region
   // after the preserved registers and before the spill areas.
   // LocalsSlotsPaddingBytes is the amount of padding between the globals and
   // locals area if they are separate.
   assert(SpillAreaAlignmentBytes <= Traits::X86_STACK_ALIGNMENT_BYTES);
@@ skipping 172 matching lines @@
 
       Variable *r15 =
           getPhysicalRegister(Traits::RegisterSet::Reg_r15, IceType_i64);
       Variable *rcx =
           getPhysicalRegister(Traits::RegisterSet::Reg_rcx, IceType_i64);
       Variable *ecx =
           getPhysicalRegister(Traits::RegisterSet::Reg_ecx, IceType_i32);
 
       _pop(rcx);
       Context.insert<InstFakeDef>(ecx, rcx);
-      _bundle_lock();
+      AutoBundle _(this);
       _mov(ebp, ecx);
 
       _redefined(Context.insert<InstFakeDef>(rbp, ebp));
       _add(rbp, r15);
-      _bundle_unlock();
     }
   }
 
   // Add pop instructions for preserved registers.
   llvm::SmallBitVector CalleeSaves =
       getRegisterSet(RegSet_CalleeSave, RegSet_None);
   llvm::SmallBitVector Popped(CalleeSaves.size());
   for (int32_t i = CalleeSaves.size() - 1; i >= 0; --i) {
     if (i == Traits::RegisterSet::Reg_rbp && IsEbpBasedFrame)
       continue;
@@ skipping 14 matching lines @@
 
   Variable *T_rcx = makeReg(IceType_i64, Traits::RegisterSet::Reg_rcx);
   Variable *T_ecx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ecx);
   _pop(T_rcx);
   _mov(T_ecx, T_rcx);
 
   // lowerIndirectJump(T_ecx);
   Variable *r15 =
       getPhysicalRegister(Traits::RegisterSet::Reg_r15, IceType_i64);
 
-  _bundle_lock();
-  const SizeT BundleSize = 1
-                           << Func->getAssembler<>()->getBundleAlignLog2Bytes();
-  _and(T_ecx, Ctx->getConstantInt32(~(BundleSize - 1)));
-  Context.insert<InstFakeDef>(T_rcx, T_ecx);
-  _add(T_rcx, r15);
+  /* AutoBundle scoping */ {
+    AutoBundle _(this);
+    const SizeT BundleSize =
+        1 << Func->getAssembler<>()->getBundleAlignLog2Bytes();
+    _and(T_ecx, Ctx->getConstantInt32(~(BundleSize - 1)));
+    Context.insert<InstFakeDef>(T_rcx, T_ecx);
+    _add(T_rcx, r15);
 
-  _jmp(T_rcx);
-  _bundle_unlock();
+    _jmp(T_rcx);
+  }
 
   if (RI->getSrcSize()) {
     auto *RetValue = llvm::cast<Variable>(RI->getSrc(0));
     Context.insert<InstFakeUse>(RetValue);
   }
   RI->setDeleted();
 }
 
 void TargetX8664::emitJumpTable(const Cfg *Func,
                                 const InstJumpTable *JumpTable) const {
@@ skipping 306 matching lines @@
 #define X(tag, sizeLog2, align, elts, elty, str)                               \
   static_assert(_table1_##tag == _table2_##tag,                                \
                 "Inconsistency between ICETYPEX8664_TABLE and ICETYPE_TABLE");
 ICETYPE_TABLE
 #undef X
 } // end of namespace dummy3
 } // end of anonymous namespace
 
 } // end of namespace X8664
 } // end of namespace Ice