Subzero. RAII NaCl Bundling.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1697 matching lines @@
       } else if (auto *LdrexInstr = llvm::dyn_cast<InstARM32Ldrex>(CurInstr)) {
         constexpr bool DisallowOffsetsBecauseLdrex = false;
         if (OperandARM32Mem *LegalMem = Legalizer.legalizeMemOperand(
                 llvm::cast<OperandARM32Mem>(LdrexInstr->getSrc(0)),
                 DisallowOffsetsBecauseLdrex)) {
           Sandboxer(this)
               .ldrex(CurInstr->getDest(), LegalMem, LdrexInstr->getPredicate());
           CurInstr->setDeleted();
         }
       } else if (auto *StrInstr = llvm::dyn_cast<InstARM32Str>(CurInstr)) {
-        Sandboxer Bundle(this);
         if (OperandARM32Mem *LegalMem = Legalizer.legalizeMemOperand(
                 llvm::cast<OperandARM32Mem>(StrInstr->getSrc(1)))) {
           Sandboxer(this).str(llvm::cast<Variable>(CurInstr->getSrc(0)),
                               LegalMem, StrInstr->getPredicate());
           CurInstr->setDeleted();
         }
       } else if (auto *StrexInstr = llvm::dyn_cast<InstARM32Strex>(CurInstr)) {
         constexpr bool DisallowOffsetsBecauseStrex = false;
         if (OperandARM32Mem *LegalMem = Legalizer.legalizeMemOperand(
                 llvm::cast<OperandARM32Mem>(StrexInstr->getSrc(1)),
@@ skipping 4401 matching lines @@
     // peephole style optimizations during or before lowering have access to
     // this instruction in undeleted form. See for example
     // tryOptimizedCmpxchgCmpBr().
     Iter->second.Instr->setDead();
     ++Iter;
   }
 }
 
 TargetARM32::Sandboxer::Sandboxer(TargetARM32 *Target,
                                   InstBundleLock::Option BundleOption)
-    : Target(Target) {
-  if (Target->NeedSandboxing) {
-    Target->_bundle_lock(BundleOption);
-  }
-}
+    : Bundler(Target, BundleOption), Target(Target) {}
 
-TargetARM32::Sandboxer::~Sandboxer() {
-  if (Target->NeedSandboxing) {
-    Target->_bundle_unlock();
-  }
-}
+TargetARM32::Sandboxer::~Sandboxer() {}
 
 namespace {
 OperandARM32FlexImm *indirectBranchBicMask(Cfg *Func) {
   constexpr uint32_t Imm8 = 0xFC; // 0xC000000F
   constexpr uint32_t RotateAmt = 2;
   return OperandARM32FlexImm::create(Func, IceType_i32, Imm8, RotateAmt);
 }
 
 OperandARM32FlexImm *memOpBicMask(Cfg *Func) {
   constexpr uint32_t Imm8 = 0x0C; // 0xC0000000
@@ skipping 288 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 llvm::SmallBitVector TargetARM32::ScratchRegs;
 
 } // end of namespace ARM32
 } // end of namespace Ice