[turbofan] Implement rounding of floats on x64 and ia32 without sse4.1.

src/x64/assembler-x64.h

Index: src/x64/assembler-x64.h
diff --git a/src/x64/assembler-x64.h b/src/x64/assembler-x64.h
index 5deb7ad7c8b301db2f86024ca666ad5a7529f2cb..62a60cc2e1dfcf5fe34b3fb40594c6c5fae36d05 100644
--- a/src/x64/assembler-x64.h
+++ b/src/x64/assembler-x64.h
@@ -1080,6 +1080,8 @@ class Assembler : public AssemblerBase {
   void cvttsd2si(Register dst, XMMRegister src);
   void cvttss2siq(Register dst, XMMRegister src);
   void cvttss2siq(Register dst, const Operand& src);
+  void cvtss2siq(Register dst, XMMRegister src);
+  void cvtss2siq(Register dst, const Operand& src);
   void cvttsd2siq(Register dst, XMMRegister src);
   void cvttsd2siq(Register dst, const Operand& src);
 
@@ -1100,6 +1102,7 @@ class Assembler : public AssemblerBase {
 
   void cvtsd2si(Register dst, XMMRegister src);
   void cvtsd2siq(Register dst, XMMRegister src);
+  void cvtsd2siq(Register dst, const Operand& src);
 
   void addsd(XMMRegister dst, XMMRegister src);
   void addsd(XMMRegister dst, const Operand& src);
@@ -1142,6 +1145,9 @@ class Assembler : public AssemblerBase {
   void roundss(XMMRegister dst, XMMRegister src, RoundingMode mode);
   void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
 
+  void ldmxcsr(const Operand& dst);
+  void stmxcsr(const Operand& dst);
+
   // AVX instruction
   void vfmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
     vfmasd(0x99, dst, src1, src2);
@@ -1358,6 +1364,11 @@ class Assembler : public AssemblerBase {
     vpd(0x73, iop, dst, src);
     emit(imm8);
   }
+  void vpslld(XMMRegister dst, XMMRegister src, byte imm8) {
+    XMMRegister iop = {6};
+    vpd(0x72, iop, dst, src);
+    emit(imm8);
+  }
   void vcvtss2sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
     vsd(0x5a, dst, src1, src2, kF3, k0F, kWIG);
   }
@@ -1416,6 +1427,14 @@ class Assembler : public AssemblerBase {
     XMMRegister idst = {dst.code()};
     vsd(0x2c, idst, xmm0, src, kF3, k0F, kW1);
   }
+  void vcvtss2siq(Register dst, XMMRegister src) {
+    XMMRegister idst = {dst.code()};
+    vsd(0x2d, idst, xmm0, src, kF3, k0F, kW1);
+  }
+  void vcvtss2siq(Register dst, const Operand& src) {
+    XMMRegister idst = {dst.code()};
+    vsd(0x2d, idst, xmm0, src, kF3, k0F, kW1);
+  }
   void vcvttsd2siq(Register dst, XMMRegister src) {
     XMMRegister idst = {dst.code()};
     vsd(0x2c, idst, xmm0, src, kF2, k0F, kW1);
@@ -1424,6 +1443,14 @@ class Assembler : public AssemblerBase {
     XMMRegister idst = {dst.code()};
     vsd(0x2c, idst, xmm0, src, kF2, k0F, kW1);
   }
+  void vcvtsd2siq(Register dst, XMMRegister src) {
+    XMMRegister idst = {dst.code()};
+    vsd(0x2d, idst, xmm0, src, kF2, k0F, kW1);
+  }
+  void vcvtsd2siq(Register dst, const Operand& src) {
+    XMMRegister idst = {dst.code()};
+    vsd(0x2d, idst, xmm0, src, kF2, k0F, kW1);
+  }
   void vcvtsd2si(Register dst, XMMRegister src) {
     XMMRegister idst = {dst.code()};
     vsd(0x2d, idst, xmm0, src, kF2, k0F, kW0);