[turbofan] Implement rounding of floats on x64 and ia32 without sse4.1.

src/x64/macro-assembler-x64.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #if V8_TARGET_ARCH_X64
 
 #include "src/base/bits.h"
 #include "src/base/division-by-constant.h"
 #include "src/bootstrapper.h"
 #include "src/codegen.h"
@@ skipping 984 matching lines @@
 void MacroAssembler::Cvttss2siq(Register dst, const Operand& src) {
   if (CpuFeatures::IsSupported(AVX)) {
     CpuFeatureScope scope(this, AVX);
     vcvttss2siq(dst, src);
   } else {
     cvttss2siq(dst, src);
   }
 }
 
 
+void MacroAssembler::Cvtss2siq(Register dst, XMMRegister src) {
+  if (CpuFeatures::IsSupported(AVX)) {
+    CpuFeatureScope scope(this, AVX);
+    vcvtss2siq(dst, src);
+  } else {
+    cvtss2siq(dst, src);
+  }
+}
+
+
+void MacroAssembler::Cvtss2siq(Register dst, const Operand& src) {
+  if (CpuFeatures::IsSupported(AVX)) {
+    CpuFeatureScope scope(this, AVX);
+    vcvtss2siq(dst, src);
+  } else {
+    cvtss2siq(dst, src);
+  }
+}
+
+
+void MacroAssembler::Cvtsd2siq(Register dst, XMMRegister src) {
+  if (CpuFeatures::IsSupported(AVX)) {
+    CpuFeatureScope scope(this, AVX);
+    vcvtsd2siq(dst, src);
+  } else {
+    cvtsd2siq(dst, src);
+  }
+}
+
+
+void MacroAssembler::Cvtsd2siq(Register dst, const Operand& src) {
+  if (CpuFeatures::IsSupported(AVX)) {
+    CpuFeatureScope scope(this, AVX);
+    vcvtsd2siq(dst, src);
+  } else {
+    cvtsd2siq(dst, src);
+  }
+}
+
+
 void MacroAssembler::Cvttsd2siq(Register dst, XMMRegister src) {
   if (CpuFeatures::IsSupported(AVX)) {
     CpuFeatureScope scope(this, AVX);
     vcvttsd2siq(dst, src);
   } else {
     cvttsd2siq(dst, src);
   }
 }
 
 
@@ skipping 1794 matching lines @@
                              RoundingMode mode) {
   if (CpuFeatures::IsSupported(AVX)) {
     CpuFeatureScope scope(this, AVX);
     vroundss(dst, dst, src, mode);
   } else {
     roundss(dst, src, mode);
   }
 }
 
 
+void MacroAssembler::Roundss(XMMRegister dst, XMMRegister src, Register tmp,
+                             XMMRegister xtmp, RoundingMode mode) {
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    CpuFeatureScope scope(this, SSE4_1);
+    Roundss(dst, src, mode);
+  } else {
+    {
+      // Set the right rounding mode.
+      subq(rsp, Immediate(kPointerSize * 2));
+      stmxcsr(Operand(rsp, 0));
+      movl(tmp, Operand(rsp, 0));
+      andl(tmp, Immediate(0xffff9fff));
+      orl(tmp, Immediate(mode << 13));
+      movl(Operand(rsp, kPointerSize), tmp);
+      ldmxcsr(Operand(rsp, kPointerSize));
+    }
+
+    // Do rounding by conversion to int64.
+    Cvtss2siq(tmp, src);
+
+    Label done;
+    Label out_of_range;
+    cmpq(tmp, Immediate(1));
+    // If the conversion results in INT64_MIN, then the input is outside
+    // int64 range, and due to the limited precision of float32 this means
+    // that the input must have been an integer already. We are therefore
+    // done already.
+    j(overflow, &out_of_range);
+
+    // Saving the sign bit.
+    Pcmpeqd(xtmp, xtmp);
+    Pslld(xtmp, 31);
+    Andps(xtmp, src);
+    // Rounding is done by converting the value back to float.
+    Cvtqsi2ss(dst, tmp);
+    // Restore the sign bit.
+    Orps(dst, xtmp);
+    if (!dst.is(src)) {
+      jmp(&done);
+    }
+
+    bind(&out_of_range);
+    if (!dst.is(src)) {
+      movss(dst, src);
+    }
+
+    bind(&done);
+    // Restore the original rounding mode.
+    ldmxcsr(Operand(rsp, 0));
+    addq(rsp, Immediate(kPointerSize * 2));
+  }
+}
+
+
 void MacroAssembler::Roundsd(XMMRegister dst, XMMRegister src,
                              RoundingMode mode) {
   if (CpuFeatures::IsSupported(AVX)) {
     CpuFeatureScope scope(this, AVX);
     vroundsd(dst, dst, src, mode);
   } else {
     roundsd(dst, src, mode);
   }
 }
 
 
+void MacroAssembler::Roundsd(XMMRegister dst, XMMRegister src, Register tmp,
+                             XMMRegister xtmp, RoundingMode mode) {
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    CpuFeatureScope scope(this, SSE4_1);
+    Roundsd(dst, src, mode);
+  } else {
+    {
+      // Set the right rounding mode.
+      subq(rsp, Immediate(kPointerSize * 2));
+      stmxcsr(Operand(rsp, 0));
+      movl(tmp, Operand(rsp, 0));
+      andl(tmp, Immediate(0xffff9fff));
+      orl(tmp, Immediate(mode << 13));
+      movl(Operand(rsp, kPointerSize), tmp);
+      ldmxcsr(Operand(rsp, kPointerSize));
+    }
+    // Do rounding by conversion to int64.
+    Cvtsd2siq(tmp, src);
+
+    Label out_of_range;
+    Label done;
+    cmpq(tmp, Immediate(1));
+    // If the conversion results in INT64_MIN, then the input is outside
+    // int64 range, and due to the limited precision of float64 this means
+    // that the input must have been an integer already. We are therefore
+    // done already.
+    j(overflow, &out_of_range);
+    // Saving the sign bit.
+    // Initialize xtmp with 0x8000000000000000.
+    Pcmpeqd(xtmp, xtmp);
+    Psllq(xtmp, 63);
+    Andpd(xtmp, src);
+    // Rounding is done by converting the value back to float.
+    Cvtqsi2sd(dst, tmp);
+    // Restore the sign bit.
+    Orpd(dst, xtmp);
+
+    if (!dst.is(src)) {
+      jmp(&done);
+    }
+
+    bind(&out_of_range);
+    if (!dst.is(src)) {
+      movsd(dst, src);
+    }
+
+    bind(&done);
+    // Restore the original rounding mode.
+    ldmxcsr(Operand(rsp, 0));
+    addq(rsp, Immediate(kPointerSize * 2));
+  }
+}
+
+
 void MacroAssembler::Sqrtsd(XMMRegister dst, XMMRegister src) {
   if (CpuFeatures::IsSupported(AVX)) {
     CpuFeatureScope scope(this, AVX);
     vsqrtsd(dst, dst, src);
   } else {
     sqrtsd(dst, src);
   }
 }
 
 
@@ skipping 2682 matching lines @@
   movl(rax, dividend);
   shrl(rax, Immediate(31));
   addl(rdx, rax);
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_X64