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Issue 1584663007: [turbofan] Implement rounding of floats on x64 and ia32 without sse4.1. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: reduced generated code. Created 4 years, 11 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/x64/assembler-x64.h" 5 #include "src/x64/assembler-x64.h"
6 6
7 #include <cstring> 7 #include <cstring>
8 8
9 #if V8_TARGET_ARCH_X64 9 #if V8_TARGET_ARCH_X64
10 10
(...skipping 3112 matching lines...) Expand 10 before | Expand all | Expand 10 after
3123 emit_sse_operand(dst, src); 3123 emit_sse_operand(dst, src);
3124 } 3124 }
3125 3125
3126 3126
3127 void Assembler::cvttss2siq(Register dst, const Operand& src) { 3127 void Assembler::cvttss2siq(Register dst, const Operand& src) {
3128 DCHECK(!IsEnabled(AVX)); 3128 DCHECK(!IsEnabled(AVX));
3129 EnsureSpace ensure_space(this); 3129 EnsureSpace ensure_space(this);
3130 emit(0xF3); 3130 emit(0xF3);
3131 emit_rex_64(dst, src); 3131 emit_rex_64(dst, src);
3132 emit(0x0F); 3132 emit(0x0F);
3133 emit(0x2D);
3134 emit_sse_operand(dst, src);
3135 }
3136
3137
3138 void Assembler::cvtss2siq(Register dst, XMMRegister src) {
3139 DCHECK(!IsEnabled(AVX));
3140 EnsureSpace ensure_space(this);
3141 emit(0xF3);
3142 emit_rex_64(dst, src);
3143 emit(0x0F);
3144 emit(0x2D);
3145 emit_sse_operand(dst, src);
3146 }
3147
3148
3149 void Assembler::cvtss2siq(Register dst, const Operand& src) {
3150 DCHECK(!IsEnabled(AVX));
3151 EnsureSpace ensure_space(this);
3152 emit(0xF3);
3153 emit_rex_64(dst, src);
3154 emit(0x0F);
3133 emit(0x2C); 3155 emit(0x2C);
3134 emit_sse_operand(dst, src); 3156 emit_sse_operand(dst, src);
3135 } 3157 }
3136 3158
3137 3159
3138 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { 3160 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
3139 DCHECK(!IsEnabled(AVX)); 3161 DCHECK(!IsEnabled(AVX));
3140 EnsureSpace ensure_space(this); 3162 EnsureSpace ensure_space(this);
3141 emit(0xF2); 3163 emit(0xF2);
3142 emit_rex_64(dst, src); 3164 emit_rex_64(dst, src);
(...skipping 160 matching lines...) Expand 10 before | Expand all | Expand 10 after
3303 DCHECK(!IsEnabled(AVX)); 3325 DCHECK(!IsEnabled(AVX));
3304 EnsureSpace ensure_space(this); 3326 EnsureSpace ensure_space(this);
3305 emit(0xF2); 3327 emit(0xF2);
3306 emit_rex_64(dst, src); 3328 emit_rex_64(dst, src);
3307 emit(0x0F); 3329 emit(0x0F);
3308 emit(0x2D); 3330 emit(0x2D);
3309 emit_sse_operand(dst, src); 3331 emit_sse_operand(dst, src);
3310 } 3332 }
3311 3333
3312 3334
3335 void Assembler::cvtsd2siq(Register dst, const Operand& src) {
3336 DCHECK(!IsEnabled(AVX));
3337 EnsureSpace ensure_space(this);
3338 emit(0xF2);
3339 emit_rex_64(dst, src);
3340 emit(0x0F);
3341 emit(0x2D);
3342 emit_sse_operand(dst, src);
3343 }
3344
3345
3313 void Assembler::addsd(XMMRegister dst, XMMRegister src) { 3346 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
3314 EnsureSpace ensure_space(this); 3347 EnsureSpace ensure_space(this);
3315 emit(0xF2); 3348 emit(0xF2);
3316 emit_optional_rex_32(dst, src); 3349 emit_optional_rex_32(dst, src);
3317 emit(0x0F); 3350 emit(0x0F);
3318 emit(0x58); 3351 emit(0x58);
3319 emit_sse_operand(dst, src); 3352 emit_sse_operand(dst, src);
3320 } 3353 }
3321 3354
3322 3355
(...skipping 216 matching lines...) Expand 10 before | Expand all | Expand 10 after
3539 emit_optional_rex_32(dst, src); 3572 emit_optional_rex_32(dst, src);
3540 emit(0x0f); 3573 emit(0x0f);
3541 emit(0x3a); 3574 emit(0x3a);
3542 emit(0x0b); 3575 emit(0x0b);
3543 emit_sse_operand(dst, src); 3576 emit_sse_operand(dst, src);
3544 // Mask precision exception. 3577 // Mask precision exception.
3545 emit(static_cast<byte>(mode) | 0x8); 3578 emit(static_cast<byte>(mode) | 0x8);
3546 } 3579 }
3547 3580
3548 3581
3582 void Assembler::ldmxcsr(const Operand& dst) {
3583 EnsureSpace ensure_space(this);
3584 emit(0x0F);
3585 emit(0xAE);
3586 emit_operand(2, dst);
3587 }
3588
3589
3590 void Assembler::stmxcsr(const Operand& dst) {
3591 EnsureSpace ensure_space(this);
3592 emit(0x0F);
3593 emit(0xAE);
3594 emit_operand(3, dst);
3595 }
3596
3597
3549 void Assembler::movmskpd(Register dst, XMMRegister src) { 3598 void Assembler::movmskpd(Register dst, XMMRegister src) {
3550 EnsureSpace ensure_space(this); 3599 EnsureSpace ensure_space(this);
3551 emit(0x66); 3600 emit(0x66);
3552 emit_optional_rex_32(dst, src); 3601 emit_optional_rex_32(dst, src);
3553 emit(0x0f); 3602 emit(0x0f);
3554 emit(0x50); 3603 emit(0x50);
3555 emit_sse_operand(dst, src); 3604 emit_sse_operand(dst, src);
3556 } 3605 }
3557 3606
3558 3607
(...skipping 590 matching lines...) Expand 10 before | Expand all | Expand 10 after
4149 4198
4150 bool RelocInfo::IsInConstantPool() { 4199 bool RelocInfo::IsInConstantPool() {
4151 return false; 4200 return false;
4152 } 4201 }
4153 4202
4154 4203
4155 } // namespace internal 4204 } // namespace internal
4156 } // namespace v8 4205 } // namespace v8
4157 4206
4158 #endif // V8_TARGET_ARCH_X64 4207 #endif // V8_TARGET_ARCH_X64
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