[turbofan] Implement rounding of floats on x64 and ia32 without sse4.1.

src/ia32/assembler-ia32.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 1964 matching lines @@
 
 void Assembler::cvttss2si(Register dst, const Operand& src) {
   EnsureSpace ensure_space(this);
   EMIT(0xF3);
   EMIT(0x0F);
   EMIT(0x2C);
   emit_operand(dst, src);
 }
 
 
+void Assembler::cvtss2si(Register dst, const Operand& src) {
+  EnsureSpace ensure_space(this);
+  EMIT(0xF3);
+  EMIT(0x0F);
+  EMIT(0x2D);
+  emit_operand(dst, src);
+}
+
+
 void Assembler::cvttsd2si(Register dst, const Operand& src) {
   EnsureSpace ensure_space(this);
   EMIT(0xF2);
   EMIT(0x0F);
   EMIT(0x2C);
   emit_operand(dst, src);
 }
 
 
+void Assembler::cvtsd2si(Register dst, const Operand& src) {
+  EnsureSpace ensure_space(this);
+  EMIT(0xF2);
+  EMIT(0x0F);
+  EMIT(0x2D);
+  emit_operand(dst, src);
+}
+
+
 void Assembler::cvtsd2si(Register dst, XMMRegister src) {
   EnsureSpace ensure_space(this);
   EMIT(0xF2);
   EMIT(0x0F);
   EMIT(0x2D);
   emit_sse_operand(dst, src);
 }
 
 
+void Assembler::cvtsi2ss(XMMRegister dst, const Operand& src) {
+  EnsureSpace ensure_space(this);
+  EMIT(0xF3);
+  EMIT(0x0F);
+  EMIT(0x2A);
+  emit_sse_operand(dst, src);
+}
+
+
 void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) {
   EnsureSpace ensure_space(this);
   EMIT(0xF2);
   EMIT(0x0F);
   EMIT(0x2A);
   emit_sse_operand(dst, src);
 }
 
 
 void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) {
@@ skipping 170 matching lines @@
   EMIT(0x66);
   EMIT(0x0F);
   EMIT(0x3A);
   EMIT(0x0B);
   emit_sse_operand(dst, src);
   // Mask precision exeption.
   EMIT(static_cast<byte>(mode) | 0x8);
 }
 
 
+void Assembler::ldmxcsr(const Operand& dst) {
+  EnsureSpace ensure_space(this);
+  EMIT(0x0F);
+  EMIT(0xAE);
+  emit_operand(2, dst);
+}
+
+
+void Assembler::stmxcsr(const Operand& dst) {
+  EnsureSpace ensure_space(this);
+  EMIT(0x0F);
+  EMIT(0xAE);
+  emit_operand(3, dst);
+}
+
+
 void Assembler::movmskpd(Register dst, XMMRegister src) {
   EnsureSpace ensure_space(this);
   EMIT(0x66);
   EMIT(0x0F);
   EMIT(0x50);
   emit_sse_operand(dst, src);
 }
 
 
 void Assembler::movmskps(Register dst, XMMRegister src) {
@@ skipping 630 matching lines @@
     emit(x);
   } else {
     EMIT(0x81);  // using a literal 32-bit immediate.
     emit_operand(ireg, dst);
     emit(x);
   }
 }
 
 
 void Assembler::emit_operand(Register reg, const Operand& adr) {
+  emit_operand(reg.code(), adr);
+}
+
+
+void Assembler::emit_operand(int code, const Operand& adr) {
+  DCHECK(is_uint3(code));
   const unsigned length = adr.len_;
   DCHECK(length > 0);
 
   // Emit updated ModRM byte containing the given register.
-  pc_[0] = (adr.buf_[0] & ~0x38) | (reg.code() << 3);
+  pc_[0] = (adr.buf_[0] & ~0x38) | (code << 3);
 
   // Emit the rest of the encoded operand.
   for (unsigned i = 1; i < length; i++) pc_[i] = adr.buf_[i];
   pc_ += length;
 
   // Emit relocation information if necessary.
   if (length >= sizeof(int32_t) && !RelocInfo::IsNone(adr.rmode_)) {
     pc_ -= sizeof(int32_t);  // pc_ must be *at* disp32
     RecordRelocInfo(adr.rmode_);
     if (adr.rmode_ == RelocInfo::INTERNAL_REFERENCE) {  // Fixup for labels
@@ skipping 82 matching lines @@
     fflush(coverage_log);
   }
 }
 
 #endif
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_IA32