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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1377 void vcvtqsi2ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { | 1377 void vcvtqsi2ss(XMMRegister dst, XMMRegister src1, const Operand& src2) { |
1378 vsd(0x2a, dst, src1, src2, kF3, k0F, kW1); | 1378 vsd(0x2a, dst, src1, src2, kF3, k0F, kW1); |
1379 } | 1379 } |
1380 void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, Register src2) { | 1380 void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, Register src2) { |
1381 XMMRegister isrc2 = {src2.code()}; | 1381 XMMRegister isrc2 = {src2.code()}; |
1382 vsd(0x2a, dst, src1, isrc2, kF2, k0F, kW1); | 1382 vsd(0x2a, dst, src1, isrc2, kF2, k0F, kW1); |
1383 } | 1383 } |
1384 void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { | 1384 void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, const Operand& src2) { |
1385 vsd(0x2a, dst, src1, src2, kF2, k0F, kW1); | 1385 vsd(0x2a, dst, src1, src2, kF2, k0F, kW1); |
1386 } | 1386 } |
| 1387 void vcvttss2si(Register dst, XMMRegister src) { |
| 1388 XMMRegister idst = {dst.code()}; |
| 1389 vsd(0x2c, idst, xmm0, src, kF3, k0F, kW0); |
| 1390 } |
| 1391 void vcvttss2si(Register dst, const Operand& src) { |
| 1392 XMMRegister idst = {dst.code()}; |
| 1393 vsd(0x2c, idst, xmm0, src, kF3, k0F, kW0); |
| 1394 } |
1387 void vcvttsd2si(Register dst, XMMRegister src) { | 1395 void vcvttsd2si(Register dst, XMMRegister src) { |
1388 XMMRegister idst = {dst.code()}; | 1396 XMMRegister idst = {dst.code()}; |
1389 vsd(0x2c, idst, xmm0, src, kF2, k0F, kW0); | 1397 vsd(0x2c, idst, xmm0, src, kF2, k0F, kW0); |
1390 } | 1398 } |
1391 void vcvttsd2si(Register dst, const Operand& src) { | 1399 void vcvttsd2si(Register dst, const Operand& src) { |
1392 XMMRegister idst = {dst.code()}; | 1400 XMMRegister idst = {dst.code()}; |
1393 vsd(0x2c, idst, xmm0, src, kF2, k0F, kW0); | 1401 vsd(0x2c, idst, xmm0, src, kF2, k0F, kW0); |
1394 } | 1402 } |
1395 void vcvttss2siq(Register dst, XMMRegister src) { | 1403 void vcvttss2siq(Register dst, XMMRegister src) { |
1396 XMMRegister idst = {dst.code()}; | 1404 XMMRegister idst = {dst.code()}; |
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2189 Assembler* assembler_; | 2197 Assembler* assembler_; |
2190 #ifdef DEBUG | 2198 #ifdef DEBUG |
2191 int space_before_; | 2199 int space_before_; |
2192 #endif | 2200 #endif |
2193 }; | 2201 }; |
2194 | 2202 |
2195 } // namespace internal | 2203 } // namespace internal |
2196 } // namespace v8 | 2204 } // namespace v8 |
2197 | 2205 |
2198 #endif // V8_X64_ASSEMBLER_X64_H_ | 2206 #endif // V8_X64_ASSEMBLER_X64_H_ |
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