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Issue 1583323004: [turbofan] Add the TruncateFloat32ToInt32 operator to turbofan. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Fixed a small bug Created 4 years, 11 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 60 matching lines...) Expand 10 before | Expand all | Expand 10 after
71 V(ArmVrintpF64) \ 71 V(ArmVrintpF64) \
72 V(ArmVrintzF32) \ 72 V(ArmVrintzF32) \
73 V(ArmVrintzF64) \ 73 V(ArmVrintzF64) \
74 V(ArmVrintaF64) \ 74 V(ArmVrintaF64) \
75 V(ArmVrintnF32) \ 75 V(ArmVrintnF32) \
76 V(ArmVrintnF64) \ 76 V(ArmVrintnF64) \
77 V(ArmVcvtF32F64) \ 77 V(ArmVcvtF32F64) \
78 V(ArmVcvtF64F32) \ 78 V(ArmVcvtF64F32) \
79 V(ArmVcvtF64S32) \ 79 V(ArmVcvtF64S32) \
80 V(ArmVcvtF64U32) \ 80 V(ArmVcvtF64U32) \
81 V(ArmVcvtS32F32) \
81 V(ArmVcvtS32F64) \ 82 V(ArmVcvtS32F64) \
82 V(ArmVcvtU32F64) \ 83 V(ArmVcvtU32F64) \
83 V(ArmVmovLowU32F64) \ 84 V(ArmVmovLowU32F64) \
84 V(ArmVmovLowF64U32) \ 85 V(ArmVmovLowF64U32) \
85 V(ArmVmovHighU32F64) \ 86 V(ArmVmovHighU32F64) \
86 V(ArmVmovHighF64U32) \ 87 V(ArmVmovHighF64U32) \
87 V(ArmVmovF64U32U32) \ 88 V(ArmVmovF64U32U32) \
88 V(ArmVldrF32) \ 89 V(ArmVldrF32) \
89 V(ArmVstrF32) \ 90 V(ArmVstrF32) \
90 V(ArmVldrF64) \ 91 V(ArmVldrF64) \
(...skipping 26 matching lines...) Expand all
117 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ 118 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
118 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ 119 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
119 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ 120 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
120 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ 121 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
121 122
122 } // namespace compiler 123 } // namespace compiler
123 } // namespace internal 124 } // namespace internal
124 } // namespace v8 125 } // namespace v8
125 126
126 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 127 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
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