| OLD | NEW |
| 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 // All Rights Reserved. | 2 // All Rights Reserved. |
| 3 // | 3 // |
| 4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
| 5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
| 6 // are met: | 6 // are met: |
| 7 // | 7 // |
| 8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
| 9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
| 10 // | 10 // |
| (...skipping 2905 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 2916 | 2916 |
| 2917 | 2917 |
| 2918 void Assembler::vcvt_f64_u32(const DwVfpRegister dst, | 2918 void Assembler::vcvt_f64_u32(const DwVfpRegister dst, |
| 2919 const SwVfpRegister src, | 2919 const SwVfpRegister src, |
| 2920 VFPConversionMode mode, | 2920 VFPConversionMode mode, |
| 2921 const Condition cond) { | 2921 const Condition cond) { |
| 2922 emit(EncodeVCVT(F64, dst.code(), U32, src.code(), mode, cond)); | 2922 emit(EncodeVCVT(F64, dst.code(), U32, src.code(), mode, cond)); |
| 2923 } | 2923 } |
| 2924 | 2924 |
| 2925 | 2925 |
| 2926 void Assembler::vcvt_s32_f32(const SwVfpRegister dst, const SwVfpRegister src, |
| 2927 VFPConversionMode mode, const Condition cond) { |
| 2928 emit(EncodeVCVT(S32, dst.code(), F32, src.code(), mode, cond)); |
| 2929 } |
| 2930 |
| 2931 |
| 2926 void Assembler::vcvt_s32_f64(const SwVfpRegister dst, | 2932 void Assembler::vcvt_s32_f64(const SwVfpRegister dst, |
| 2927 const DwVfpRegister src, | 2933 const DwVfpRegister src, |
| 2928 VFPConversionMode mode, | 2934 VFPConversionMode mode, |
| 2929 const Condition cond) { | 2935 const Condition cond) { |
| 2930 emit(EncodeVCVT(S32, dst.code(), F64, src.code(), mode, cond)); | 2936 emit(EncodeVCVT(S32, dst.code(), F64, src.code(), mode, cond)); |
| 2931 } | 2937 } |
| 2932 | 2938 |
| 2933 | 2939 |
| 2934 void Assembler::vcvt_u32_f64(const SwVfpRegister dst, | 2940 void Assembler::vcvt_u32_f64(const SwVfpRegister dst, |
| 2935 const DwVfpRegister src, | 2941 const DwVfpRegister src, |
| (...skipping 1169 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 4105 DCHECK(is_uint12(offset)); | 4111 DCHECK(is_uint12(offset)); |
| 4106 instr_at_put(pc, SetLdrRegisterImmediateOffset(instr, offset)); | 4112 instr_at_put(pc, SetLdrRegisterImmediateOffset(instr, offset)); |
| 4107 } | 4113 } |
| 4108 } | 4114 } |
| 4109 | 4115 |
| 4110 | 4116 |
| 4111 } // namespace internal | 4117 } // namespace internal |
| 4112 } // namespace v8 | 4118 } // namespace v8 |
| 4113 | 4119 |
| 4114 #endif // V8_TARGET_ARCH_ARM | 4120 #endif // V8_TARGET_ARCH_ARM |
| OLD | NEW |