Implements intrinsics for ARM.

runtime/vm/assembler_arm_test.cc

Index: runtime/vm/assembler_arm_test.cc
===================================================================
--- runtime/vm/assembler_arm_test.cc	(revision 23305)
+++ runtime/vm/assembler_arm_test.cc	(working copy)
@@ -225,6 +225,25 @@
 }
 
 
+ASSEMBLER_TEST_GENERATE(DoubleSqrtNeg, assembler) {
+  // Check that sqrt of a negative double gives NaN.
+  __ LoadDImmediate(D1, -1.0, R0);
+  __ vsqrtd(D0, D1);
+  __ vcmpd(D0, D0);
+  __ vmstat();
+  __ mov(R0, ShifterOperand(1), VS);
+  __ eor(R0, R0, ShifterOperand(R0), VC);

[regis, 2013/05/28 22:01:44]

mov(R0, ShifterOperand(0), VC) may be clearer than eor.

[zra, 2013/05/28 22:49:31]

Done.

+  __ Ret();
+}
+
+
+ASSEMBLER_TEST_RUN(DoubleSqrtNeg, test) {
+  EXPECT(test != NULL);
+  typedef double (*DoubleFPOperations)();
+  EXPECT_EQ(1, EXECUTE_TEST_CODE_INT32(DoubleFPOperations, test->entry()));
+}
+
+
 ASSEMBLER_TEST_GENERATE(IntToDoubleConversion, assembler) {
   __ mov(R3, ShifterOperand(6));
   __ vmovsr(S3, R3);
@@ -650,6 +669,20 @@
 }
 
 
+ASSEMBLER_TEST_GENERATE(MultiplyAccum32To64, assembler) {
+  __ smlal(R0, R1, R0, R2);
+  __ mov(PC, ShifterOperand(LR));
+}
+
+
+ASSEMBLER_TEST_RUN(MultiplyAccum32To64, test) {
+  EXPECT(test != NULL);
+  typedef int64_t (*Multiply32To64)(int64_t operand0, int64_t operand1);
+  EXPECT_EQ(3,
+            EXECUTE_TEST_CODE_INT64_LL(Multiply32To64, test->entry(), -3, -2));
+}
+
+
 ASSEMBLER_TEST_GENERATE(Clz, assembler) {
   Label error;