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Side by Side Diff: runtime/vm/disassembler_arm.cc

Issue 15822008: Implements intrinsics for ARM. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 6 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/disassembler.h" 5 #include "vm/disassembler.h"
6 6
7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. 7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM.
8 #if defined(TARGET_ARCH_ARM) 8 #if defined(TARGET_ARCH_ARM)
9 #include "platform/assert.h" 9 #include "platform/assert.h"
10 10
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636 case 4: { 636 case 4: {
637 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. 637 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
638 Format(instr, "umull'cond's 'rd, 'rn, 'rm, 'rs"); 638 Format(instr, "umull'cond's 'rd, 'rn, 'rm, 'rs");
639 break; 639 break;
640 } 640 }
641 case 6: { 641 case 6: {
642 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. 642 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
643 Format(instr, "smull'cond's 'rd, 'rn, 'rm, 'rs"); 643 Format(instr, "smull'cond's 'rd, 'rn, 'rm, 'rs");
644 break; 644 break;
645 } 645 }
646 case 7: {
647 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
648 Format(instr, "smlal'cond's 'rd, 'rn, 'rm, 'rs");
649 break;
650 }
646 default: { 651 default: {
647 Unknown(instr); // Not used. 652 Unknown(instr); // Not used.
648 break; 653 break;
649 } 654 }
650 } 655 }
651 } else { 656 } else {
652 // synchronization primitives 657 // synchronization primitives
653 switch (instr->Bits(20, 4)) { 658 switch (instr->Bits(20, 4)) {
654 case 8: { 659 case 8: {
655 Format(instr, "strex'cond 'rd, 'rm, ['rn]"); 660 Format(instr, "strex'cond 'rd, 'rm, ['rn]");
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1306 human_buffer, 1311 human_buffer,
1307 sizeof(human_buffer), 1312 sizeof(human_buffer),
1308 pc); 1313 pc);
1309 pc += instruction_length; 1314 pc += instruction_length;
1310 } 1315 }
1311 } 1316 }
1312 1317
1313 } // namespace dart 1318 } // namespace dart
1314 1319
1315 #endif // defined TARGET_ARCH_ARM 1320 #endif // defined TARGET_ARCH_ARM
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