Implements intrinsics for ARM.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/simulator.h"
 #include "vm/runtime_entry.h"
 #include "vm/stub_code.h"
 
 // An extra check since we are assuming the existence of /proc/cpuinfo below.
 #if !defined(USING_SIMULATOR) && !defined(__linux__)
 #error ARM cross-compile only supported on Linux
 #endif
 
 namespace dart {
 
 DEFINE_FLAG(bool, print_stop_message, true, "Print stop message.");
-
+DECLARE_FLAG(bool, inline_alloc);
 
 bool CPUFeatures::integer_division_supported_ = false;
 #if defined(DEBUG)
 bool CPUFeatures::initialized_ = false;
 #endif
 
 
 bool CPUFeatures::integer_division_supported() {
   DEBUG_ASSERT(initialized_);
   return integer_division_supported_;
@@ skipping 375 matching lines @@
   EmitType01(cond, so.type(), MOV, 1, R0, rd, so);
 }
 
 
 void Assembler::bic(Register rd, Register rn, ShifterOperand so,
                     Condition cond) {
   EmitType01(cond, so.type(), BIC, 0, rn, rd, so);
 }
 
 
+void Assembler::bics(Register rd, Register rn, ShifterOperand so,
+                     Condition cond) {
+  EmitType01(cond, so.type(), BIC, 1, rn, rd, so);
+}
+
+
 void Assembler::mvn(Register rd, ShifterOperand so, Condition cond) {
   EmitType01(cond, so.type(), MVN, 0, R0, rd, so);
 }
 
 
 void Assembler::mvns(Register rd, ShifterOperand so, Condition cond) {
   EmitType01(cond, so.type(), MVN, 1, R0, rd, so);
 }
 
 
@@ skipping 83 matching lines @@
 }
 
 
 void Assembler::umull(Register rd_lo, Register rd_hi,
                       Register rn, Register rm, Condition cond) {
   // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
   EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm);
 }
 
 
+void Assembler::smlal(Register rd_lo, Register rd_hi,
+                      Register rn, Register rm, Condition cond) {
+  // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
+  EmitMulOp(cond, B23 | B22 | B21, rd_lo, rd_hi, rn, rm);
+}
+
+
 void Assembler::EmitDivOp(Condition cond, int32_t opcode,
                           Register rd, Register rn, Register rm) {
   ASSERT(CPUFeatures::integer_division_supported());
   ASSERT(rd != kNoRegister);
   ASSERT(rn != kNoRegister);
   ASSERT(rm != kNoRegister);
   ASSERT(cond != kNoCondition);
   int32_t encoding = opcode |
     (static_cast<int32_t>(cond) << kConditionShift) |
     (static_cast<int32_t>(rn) << kDivRnShift) |
@@ skipping 1523 matching lines @@
     regs |= (1 << PP);
   }
   LeaveFrame(regs);
   // Adjust SP for null PC pushed in EnterStubFrame.
   AddImmediate(SP, kWordSize);
 }
 
 
 void Assembler::TryAllocate(const Class& cls,
                             Label* failure,
-                            bool near_jump,
                             Register instance_reg) {
-  UNIMPLEMENTED();
+  ASSERT(failure != NULL);
+  if (FLAG_inline_alloc) {
+    Heap* heap = Isolate::Current()->heap();
+    const intptr_t instance_size = cls.instance_size();
+    LoadImmediate(instance_reg, heap->TopAddress());
+    ldr(instance_reg, Address(instance_reg, 0));
+    AddImmediate(instance_reg, instance_size);
+
+    // instance_reg: potential next object start.
+    LoadImmediate(TMP, heap->EndAddress());
+    ldr(TMP, Address(TMP, 0));
+    cmp(TMP, ShifterOperand(instance_reg));
+    // fail if heap end unsigned less than or equal to instance_reg.
+    b(failure, LS);
+
+    // Successfully allocated the object, now update top to point to
+    // next object start and store the class in the class field of object.
+    LoadImmediate(TMP, heap->TopAddress());
+    str(instance_reg, Address(TMP, 0));
+
+    ASSERT(instance_size >= kHeapObjectTag);
+    AddImmediate(instance_reg, -instance_size + kHeapObjectTag);
+
+    uword tags = 0;
+    tags = RawObject::SizeTag::update(instance_size, tags);
+    ASSERT(cls.id() != kIllegalCid);
+    tags = RawObject::ClassIdTag::update(cls.id(), tags);
+    LoadImmediate(TMP, tags);
+    str(TMP, FieldAddress(instance_reg, Object::tags_offset()));
+  } else {
+    b(failure);
+  }
 }
 
 
 void Assembler::Stop(const char* message) {
   if (FLAG_print_stop_message) {
     PushList((1 << R0) | (1 << IP) | (1 << LR));  // Preserve R0, IP, LR.
     LoadImmediate(R0, reinterpret_cast<int32_t>(message));
     // PrintStopMessage() preserves all registers.
     BranchLink(&StubCode::PrintStopMessageLabel());  // Passing message in R0.
     PopList((1 << R0) | (1 << IP) | (1 << LR));  // Restore R0, IP, LR.
@@ skipping 87 matching lines @@
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM