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Side by Side Diff: src/IceTargetLoweringARM32.h

Issue 1581803009: Make RegARM32 a namespace rather than a class. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nits. Created 4 years, 11 months ago
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1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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1005 TargetARM32Features CPUFeatures; 1005 TargetARM32Features CPUFeatures;
1006 bool UsesFramePointer = false; 1006 bool UsesFramePointer = false;
1007 bool NeedsStackAlignment = false; 1007 bool NeedsStackAlignment = false;
1008 bool MaybeLeafFunc = true; 1008 bool MaybeLeafFunc = true;
1009 size_t SpillAreaSizeBytes = 0; 1009 size_t SpillAreaSizeBytes = 0;
1010 size_t FixedAllocaSizeBytes = 0; 1010 size_t FixedAllocaSizeBytes = 0;
1011 size_t FixedAllocaAlignBytes = 0; 1011 size_t FixedAllocaAlignBytes = 0;
1012 bool PrologEmitsFixedAllocas = false; 1012 bool PrologEmitsFixedAllocas = false;
1013 uint32_t MaxOutArgsSizeBytes = 0; 1013 uint32_t MaxOutArgsSizeBytes = 0;
1014 // TODO(jpp): std::array instead of array. 1014 // TODO(jpp): std::array instead of array.
1015 static llvm::SmallBitVector TypeToRegisterSet[RCARM32_NUM]; 1015 static llvm::SmallBitVector TypeToRegisterSet[RegARM32::RCARM32_NUM];
1016 static llvm::SmallBitVector RegisterAliases[RegARM32::Reg_NUM]; 1016 static llvm::SmallBitVector RegisterAliases[RegARM32::Reg_NUM];
1017 static llvm::SmallBitVector ScratchRegs; 1017 static llvm::SmallBitVector ScratchRegs;
1018 llvm::SmallBitVector RegsUsed; 1018 llvm::SmallBitVector RegsUsed;
1019 VarList PhysicalRegisters[IceType_NUM]; 1019 VarList PhysicalRegisters[IceType_NUM];
1020 VarList PreservedGPRs; 1020 VarList PreservedGPRs;
1021 VarList PreservedSRegs; 1021 VarList PreservedSRegs;
1022 1022
1023 /// Helper class that understands the Calling Convention and register 1023 /// Helper class that understands the Calling Convention and register
1024 /// assignments. The first few integer type parameters can use r0-r3, 1024 /// assignments. The first few integer type parameters can use r0-r3,
1025 /// regardless of their position relative to the floating-point/vector 1025 /// regardless of their position relative to the floating-point/vector
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1202 private: 1202 private:
1203 ~TargetHeaderARM32() = default; 1203 ~TargetHeaderARM32() = default;
1204 1204
1205 TargetARM32Features CPUFeatures; 1205 TargetARM32Features CPUFeatures;
1206 }; 1206 };
1207 1207
1208 } // end of namespace ARM32 1208 } // end of namespace ARM32
1209 } // end of namespace Ice 1209 } // end of namespace Ice
1210 1210
1211 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H 1211 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H
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