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| 1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===// | 1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 750 return; | 750 return; |
| 751 Ostream &Str = Func->getContext()->getStrEmit(); | 751 Ostream &Str = Func->getContext()->getStrEmit(); |
| 752 Str << "\t" << getSRegOpcode() << "\t{"; | 752 Str << "\t" << getSRegOpcode() << "\t{"; |
| 753 bool IsFirst = true; | 753 bool IsFirst = true; |
| 754 int32_t Base = BaseReg->getRegNum(); | 754 int32_t Base = BaseReg->getRegNum(); |
| 755 for (SizeT i = 0; i < RegCount; ++i) { | 755 for (SizeT i = 0; i < RegCount; ++i) { |
| 756 if (IsFirst) | 756 if (IsFirst) |
| 757 IsFirst = false; | 757 IsFirst = false; |
| 758 else | 758 else |
| 759 Str << ", "; | 759 Str << ", "; |
| 760 Str << RegARM32::getSRegName(Base + i); | 760 Str << RegARM32::getRegName(Base + i); |
| 761 } | 761 } |
| 762 Str << "}"; | 762 Str << "}"; |
| 763 } | 763 } |
| 764 | 764 |
| 765 namespace { | 765 namespace { |
| 766 | 766 |
| 767 bool isAssignedConsecutiveRegisters(const Variable *Before, | 767 bool isAssignedConsecutiveRegisters(const Variable *Before, |
| 768 const Variable *After) { | 768 const Variable *After) { |
| 769 assert(Before->hasReg()); | 769 assert(Before->hasReg()); |
| 770 assert(After->hasReg()); | 770 assert(After->hasReg()); |
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| 2216 | 2216 |
| 2217 template class InstARM32FourAddrGPR<InstARM32::Mla>; | 2217 template class InstARM32FourAddrGPR<InstARM32::Mla>; |
| 2218 template class InstARM32FourAddrGPR<InstARM32::Mls>; | 2218 template class InstARM32FourAddrGPR<InstARM32::Mls>; |
| 2219 | 2219 |
| 2220 template class InstARM32CmpLike<InstARM32::Cmn>; | 2220 template class InstARM32CmpLike<InstARM32::Cmn>; |
| 2221 template class InstARM32CmpLike<InstARM32::Cmp>; | 2221 template class InstARM32CmpLike<InstARM32::Cmp>; |
| 2222 template class InstARM32CmpLike<InstARM32::Tst>; | 2222 template class InstARM32CmpLike<InstARM32::Tst>; |
| 2223 | 2223 |
| 2224 } // end of namespace ARM32 | 2224 } // end of namespace ARM32 |
| 2225 } // end of namespace Ice | 2225 } // end of namespace Ice |
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