Make RegARM32 a namespace rather than a class.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 35 matching lines @@
 }
 
 std::unique_ptr<::Ice::TargetHeaderLowering>
 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) {
   return ::Ice::ARM32::TargetHeaderARM32::create(Ctx);
 }
 
 void staticInit(const ::Ice::ClFlags &Flags) {
   ::Ice::ARM32::TargetARM32::staticInit(Flags);
 }
+
 } // end of namespace ARM32
 
 namespace Ice {
 namespace ARM32 {
 
+namespace {
+
+/// SizeOf is used to obtain the size of an initializer list as a constexpr
+/// expression. This is only needed until our C++ library is updated to
+/// C++ 14 -- which defines constexpr members to std::initializer_list.
+class SizeOf {
+  SizeOf(const SizeOf &) = delete;
+  SizeOf &operator=(const SizeOf &) = delete;
+
+public:
+  constexpr SizeOf() : Size(0) {}
+  template <typename... T>
+  explicit constexpr SizeOf(T...)
+      : Size(__length<T...>::value) {}
+  constexpr SizeT size() const { return Size; }
+
+private:
+  template <typename T, typename... U> struct __length {
+    static constexpr std::size_t value = 1 + __length<U...>::value;
+  };
+
+  template <typename T> struct __length<T> {
+    static constexpr std::size_t value = 1;
+  };
+
+  const std::size_t Size;
+};
+
+} // end of anonymous namespace
+
 // Defines the RegARM32::Table table with register information.
-constexpr RegARM32::TableType RegARM32::Table[];
+RegARM32::RegTableType RegARM32::RegTable[RegARM32::Reg_NUM] = {
+#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
+          isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
+  {                                                                            \
+    name, encode, cc_arg, scratch, preserved, stackptr, frameptr, isGPR,       \
+        isInt, isI64Pair, isFP32, isFP64, isVec128,                            \
+           (SizeOf alias_init).size(), alias_init                            \

[Jim Stichnoth, 2016/01/15 01:17:15]

I assume this trailing backslash alignment will get fixed by "make format"...

[Karl, 2016/01/15 16:11:19]

Done.

+  }                                                                            \
+  ,
+    REGARM32_TABLE
+#undef X
+};
 
 namespace {
 
 // The following table summarizes the logic for lowering the icmp instruction
 // for i32 and narrower types. Each icmp condition has a clear mapping to an
 // ARM32 conditional move instruction.
 
 const struct TableIcmp32_ {
   CondARM32::Cond Mapping;
 } TableIcmp32[] = {
@@ skipping 166 matching lines @@
   (void)Flags;
   // Limit this size (or do all bitsets need to be the same width)???
   llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector I64PairRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float32Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM);
   ScratchRegs.resize(RegARM32::Reg_NUM);
   for (int i = 0; i < RegARM32::Reg_NUM; ++i) {
-    const auto &Entry = RegARM32::Table[i];
+    const auto &Entry = RegARM32::RegTable[i];
     IntegerRegisters[i] = Entry.IsInt;
     I64PairRegisters[i] = Entry.IsI64Pair;
     Float32Registers[i] = Entry.IsFP32;
     Float64Registers[i] = Entry.IsFP64;
     VectorRegisters[i] = Entry.IsVec128;
     ScratchRegs[i] = Entry.Scratch;
     RegisterAliases[i].resize(RegARM32::Reg_NUM);
     for (int j = 0; j < Entry.NumAliases; ++j) {
       assert(i == j || !RegisterAliases[i][Entry.Aliases[j]]);
       RegisterAliases[i].set(Entry.Aliases[j]);
@@ skipping 1566 matching lines @@
   }
   llvm::report_fatal_error("Unsupported operand type");
   return nullptr;
 }
 
 llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include,
                                                  RegSetMask Exclude) const {
   llvm::SmallBitVector Registers(RegARM32::Reg_NUM);
 
   for (int i = 0; i < RegARM32::Reg_NUM; ++i) {
-    const auto &Entry = RegARM32::Table[i];
+    const auto &Entry = RegARM32::RegTable[i];
     if (Entry.Scratch && (Include & RegSet_CallerSave))
       Registers[i] = true;
     if (Entry.Preserved && (Include & RegSet_CalleeSave))
       Registers[i] = true;
     if (Entry.StackPtr && (Include & RegSet_StackPointer))
       Registers[i] = true;
     if (Entry.FramePtr && (Include & RegSet_FramePointer))
       Registers[i] = true;
     if (Entry.Scratch && (Exclude & RegSet_CallerSave))
       Registers[i] = false;
@@ skipping 4602 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 llvm::SmallBitVector TargetARM32::ScratchRegs;
 
 } // end of namespace ARM32
 } // end of namespace Ice