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Side by Side Diff: src/compiler/arm64/code-generator-arm64.cc

Issue 1578723002: [turbofan] Build s/NULL/nullptr/g and CHECK(x != nullptr) to CHECK_NOT_NULL(x). (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 4 years, 11 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/compiler/code-generator.h" 5 #include "src/compiler/code-generator.h"
6 6
7 #include "src/arm64/frames-arm64.h" 7 #include "src/arm64/frames-arm64.h"
8 #include "src/arm64/macro-assembler-arm64.h" 8 #include "src/arm64/macro-assembler-arm64.h"
9 #include "src/ast/scopes.h" 9 #include "src/ast/scopes.h"
10 #include "src/compiler/code-generator-impl.h" 10 #include "src/compiler/code-generator-impl.h"
(...skipping 187 matching lines...) Expand 10 before | Expand all | Expand 10 after
198 return Operand(constant.ToHeapObject()); 198 return Operand(constant.ToHeapObject());
199 case Constant::kRpoNumber: 199 case Constant::kRpoNumber:
200 UNREACHABLE(); // TODO(dcarney): RPO immediates on arm64. 200 UNREACHABLE(); // TODO(dcarney): RPO immediates on arm64.
201 break; 201 break;
202 } 202 }
203 UNREACHABLE(); 203 UNREACHABLE();
204 return Operand(-1); 204 return Operand(-1);
205 } 205 }
206 206
207 MemOperand ToMemOperand(InstructionOperand* op, MacroAssembler* masm) const { 207 MemOperand ToMemOperand(InstructionOperand* op, MacroAssembler* masm) const {
208 DCHECK(op != NULL); 208 DCHECK_NOT_NULL(op);
209 DCHECK(op->IsStackSlot() || op->IsDoubleStackSlot()); 209 DCHECK(op->IsStackSlot() || op->IsDoubleStackSlot());
210 FrameOffset offset = frame_access_state()->GetFrameOffset( 210 FrameOffset offset = frame_access_state()->GetFrameOffset(
211 AllocatedOperand::cast(op)->index()); 211 AllocatedOperand::cast(op)->index());
212 if (offset.from_frame_pointer()) { 212 if (offset.from_frame_pointer()) {
213 int from_sp = 213 int from_sp =
214 offset.offset() + 214 offset.offset() +
215 ((frame()->GetSpToFpSlotCount() + frame_access_state()->sp_delta()) * 215 ((frame()->GetSpToFpSlotCount() + frame_access_state()->sp_delta()) *
216 kPointerSize); 216 kPointerSize);
217 // Convert FP-offsets to SP-offsets if it results in better code. 217 // Convert FP-offsets to SP-offsets if it results in better code.
218 if (Assembler::IsImmLSUnscaled(from_sp) || 218 if (Assembler::IsImmLSUnscaled(from_sp) ||
(...skipping 1235 matching lines...) Expand 10 before | Expand all | Expand 10 after
1454 } else if (descriptor->UseNativeStack()) { 1454 } else if (descriptor->UseNativeStack()) {
1455 pop_count += (pop_count & 1); 1455 pop_count += (pop_count & 1);
1456 } 1456 }
1457 __ Drop(pop_count); 1457 __ Drop(pop_count);
1458 __ Ret(); 1458 __ Ret();
1459 } 1459 }
1460 1460
1461 1461
1462 void CodeGenerator::AssembleMove(InstructionOperand* source, 1462 void CodeGenerator::AssembleMove(InstructionOperand* source,
1463 InstructionOperand* destination) { 1463 InstructionOperand* destination) {
1464 Arm64OperandConverter g(this, NULL); 1464 Arm64OperandConverter g(this, nullptr);
1465 // Dispatch on the source and destination operand kinds. Not all 1465 // Dispatch on the source and destination operand kinds. Not all
1466 // combinations are possible. 1466 // combinations are possible.
1467 if (source->IsRegister()) { 1467 if (source->IsRegister()) {
1468 DCHECK(destination->IsRegister() || destination->IsStackSlot()); 1468 DCHECK(destination->IsRegister() || destination->IsStackSlot());
1469 Register src = g.ToRegister(source); 1469 Register src = g.ToRegister(source);
1470 if (destination->IsRegister()) { 1470 if (destination->IsRegister()) {
1471 __ Mov(g.ToRegister(destination), src); 1471 __ Mov(g.ToRegister(destination), src);
1472 } else { 1472 } else {
1473 __ Str(src, g.ToMemOperand(destination, masm())); 1473 __ Str(src, g.ToMemOperand(destination, masm()));
1474 } 1474 }
(...skipping 76 matching lines...) Expand 10 before | Expand all | Expand 10 after
1551 __ Str(temp, g.ToMemOperand(destination, masm())); 1551 __ Str(temp, g.ToMemOperand(destination, masm()));
1552 } 1552 }
1553 } else { 1553 } else {
1554 UNREACHABLE(); 1554 UNREACHABLE();
1555 } 1555 }
1556 } 1556 }
1557 1557
1558 1558
1559 void CodeGenerator::AssembleSwap(InstructionOperand* source, 1559 void CodeGenerator::AssembleSwap(InstructionOperand* source,
1560 InstructionOperand* destination) { 1560 InstructionOperand* destination) {
1561 Arm64OperandConverter g(this, NULL); 1561 Arm64OperandConverter g(this, nullptr);
1562 // Dispatch on the source and destination operand kinds. Not all 1562 // Dispatch on the source and destination operand kinds. Not all
1563 // combinations are possible. 1563 // combinations are possible.
1564 if (source->IsRegister()) { 1564 if (source->IsRegister()) {
1565 // Register-register. 1565 // Register-register.
1566 UseScratchRegisterScope scope(masm()); 1566 UseScratchRegisterScope scope(masm());
1567 Register temp = scope.AcquireX(); 1567 Register temp = scope.AcquireX();
1568 Register src = g.ToRegister(source); 1568 Register src = g.ToRegister(source);
1569 if (destination->IsRegister()) { 1569 if (destination->IsRegister()) {
1570 Register dst = g.ToRegister(destination); 1570 Register dst = g.ToRegister(destination);
1571 __ Mov(temp, src); 1571 __ Mov(temp, src);
(...skipping 69 matching lines...) Expand 10 before | Expand all | Expand 10 after
1641 padding_size -= kInstructionSize; 1641 padding_size -= kInstructionSize;
1642 } 1642 }
1643 } 1643 }
1644 } 1644 }
1645 1645
1646 #undef __ 1646 #undef __
1647 1647
1648 } // namespace compiler 1648 } // namespace compiler
1649 } // namespace internal 1649 } // namespace internal
1650 } // namespace v8 1650 } // namespace v8
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