A64: Check that branch targets are reachable.

src/a64/assembler-a64-inl.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 866 matching lines @@
   return 0;
 }
 
 
 Instr Assembler::Cond(Condition cond) {
   return cond << Condition_offset;
 }
 
 
 Instr Assembler::ImmPCRelAddress(int imm21) {
-  ASSERT(is_int21(imm21));
+  CHECK(is_int21(imm21));
   Instr imm = static_cast<Instr>(truncate_to_int21(imm21));
   Instr immhi = (imm >> ImmPCRelLo_width) << ImmPCRelHi_offset;
   Instr immlo = imm << ImmPCRelLo_offset;
   return (immhi & ImmPCRelHi_mask) | (immlo & ImmPCRelLo_mask);
 }
 
 
 Instr Assembler::ImmUncondBranch(int imm26) {
-  ASSERT(is_int26(imm26));
+  CHECK(is_int26(imm26));
   return truncate_to_int26(imm26) << ImmUncondBranch_offset;
 }
 
 
 Instr Assembler::ImmCondBranch(int imm19) {
-  ASSERT(is_int19(imm19));
+  CHECK(is_int19(imm19));
   return truncate_to_int19(imm19) << ImmCondBranch_offset;
 }
 
 
 Instr Assembler::ImmCmpBranch(int imm19) {
-  ASSERT(is_int19(imm19));
+  CHECK(is_int19(imm19));
   return truncate_to_int19(imm19) << ImmCmpBranch_offset;
 }
 
 
 Instr Assembler::ImmTestBranch(int imm14) {
-  ASSERT(is_int14(imm14));
+  CHECK(is_int14(imm14));
   return truncate_to_int14(imm14) << ImmTestBranch_offset;
 }
 
 
 Instr Assembler::ImmTestBranchBit(unsigned bit_pos) {
   ASSERT(is_uint6(bit_pos));
   // Subtract five from the shift offset, as we need bit 5 from bit_pos.
   unsigned b5 = bit_pos << (ImmTestBranchBit5_offset - 5);
   unsigned b40 = bit_pos << ImmTestBranchBit40_offset;
   b5 &= ImmTestBranchBit5_mask;
@@ skipping 46 matching lines @@
 Instr Assembler::ImmRotate(unsigned immr, unsigned reg_size) {
   ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
   ASSERT(((reg_size == kXRegSize) && is_uint6(immr)) ||
          ((reg_size == kWRegSize) && is_uint5(immr)));
   USE(reg_size);
   return immr << ImmRotate_offset;
 }
 
 
 Instr Assembler::ImmLLiteral(int imm19) {
-  ASSERT(is_int19(imm19));
+  CHECK(is_int19(imm19));
   return truncate_to_int19(imm19) << ImmLLiteral_offset;
 }
 
 
 Instr Assembler::BitN(unsigned bitn, unsigned reg_size) {
   ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
   ASSERT((reg_size == kXRegSize) || (bitn == 0));
   USE(reg_size);
   return bitn << BitN_offset;
 }
@@ skipping 146 matching lines @@
 
 
 void Assembler::ClearRecordedAstId() {
   recorded_ast_id_ = TypeFeedbackId::None();
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_A64_ASSEMBLER_A64_INL_H_