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Unified Diff: src/mips/assembler-mips.h

Issue 1573983002: MIPS: Replace JR/JALR with JIC/JIALC for r6 (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 4 years, 11 months ago
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Index: src/mips/assembler-mips.h
diff --git a/src/mips/assembler-mips.h b/src/mips/assembler-mips.h
index fbeed471610211a67091e50244f73b5881314c7e..15783f4f233d6b64a064c71a7902993b80a90246 100644
--- a/src/mips/assembler-mips.h
+++ b/src/mips/assembler-mips.h
@@ -524,8 +524,13 @@ class Assembler : public AssemblerBase {
// the instruction that follows LUI/ORI instruction pair. Now, with new jump
// optimization, where jump-through-register instruction that usually
// follows LUI/ORI pair is substituted with J/JAL, this constant equals
paul.l... 2016/01/11 22:34:57 These comments about J/JAL should have been remove
miran.karic 2016/02/18 08:38:05 Done.
- // to 3 instructions (LUI+ORI+J/JAL/JR/JALR).
+// to 3 instructions (LUI+ORI+J/JAL/JR/JALR). On r6, 32bit constant is placed
+// in 2 instructions (LUI+JIC)
+#ifdef _MIPS_ARCH_MIPS32R6
+ static const int kInstructionsFor32BitConstant = 2;
+#else
static const int kInstructionsFor32BitConstant = 3;
paul.l... 2016/01/11 22:34:57 I _think_ this case of 3 was only useful when we h
miran.karic 2016/02/18 08:38:05 Done. New CL created.
+#endif
// Distance between the instruction referring to the address of the call
// target and the return address.
@@ -1086,6 +1091,7 @@ class Assembler : public AssemblerBase {
static bool IsBnezc(Instr instr);
static bool IsBeqc(Instr instr);
static bool IsBnec(Instr instr);
+ static bool IsJicOrJialc(Instr instr);
static bool IsJump(Instr instr);
static bool IsJ(Instr instr);
@@ -1125,12 +1131,20 @@ class Assembler : public AssemblerBase {
static int32_t GetBranchOffset(Instr instr);
static bool IsLw(Instr instr);
static int16_t GetLwOffset(Instr instr);
+ static int16_t GetJicOrJialcOffset(Instr instr);
+ static int16_t GetLuiOffset(Instr instr);
static Instr SetLwOffset(Instr instr, int16_t offset);
static bool IsSw(Instr instr);
static Instr SetSwOffset(Instr instr, int16_t offset);
static bool IsAddImmediate(Instr instr);
static Instr SetAddImmediateOffset(Instr instr, int16_t offset);
+ static uint32_t createTargetAddress(Instr instr_lui, Instr instr_jic);
+ static void unpackTargetAddress(uint32_t address, int16_t& lui_offset,
+ int16_t& jic_offset);
+ static void unpackTargetAddressUnsigned(uint32_t address,
+ uint32_t& lui_offset,
+ uint32_t& jic_offset);
static bool IsAndImmediate(Instr instr);
static bool IsEmittedConstant(Instr instr);
@@ -1211,6 +1225,8 @@ class Assembler : public AssemblerBase {
inline void CheckTrampolinePoolQuick(int extra_instructions = 0);
+ inline void CheckBuffer();
+
private:
inline static void set_target_internal_reference_encoded_at(Address pc,
Address target);
@@ -1257,7 +1273,6 @@ class Assembler : public AssemblerBase {
enum class CompactBranchType : bool { NO = false, COMPACT_BRANCH = true };
// Code emission.
- inline void CheckBuffer();
void GrowBuffer();
inline void emit(Instr x,
CompactBranchType is_compact_branch = CompactBranchType::NO);
@@ -1399,7 +1414,11 @@ class Assembler : public AssemblerBase {
// branch instruction generation, where we use jump instructions rather
// than regular branch instructions.
bool trampoline_emitted_;
+#ifdef _MIPS_ARCH_MIPS32R6
+ static const int kTrampolineSlotsSize = 2 * kInstrSize;
+#else
static const int kTrampolineSlotsSize = 4 * kInstrSize;
+#endif
static const int kMaxBranchOffset = (1 << (18 - 1)) - 1;
static const int kMaxCompactBranchOffset = (1 << (28 - 1)) - 1;
static const int kInvalidSlotPos = -1;
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