MIPS: Replace JR/JALR with JIC/JIALC for r6

src/mips/assembler-mips.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 505 matching lines @@
   // are split across two consecutive instructions and don't exist separately
   // in the code, so the serializer should not step forwards in memory after
   // a target is resolved and written.
   static const int kSpecialTargetSize = 0;
 
   // Number of consecutive instructions used to store 32bit constant.
   // Before jump-optimizations, this constant was used in
   // RelocInfo::target_address_address() function to tell serializer address of
   // the instruction that follows LUI/ORI instruction pair. Now, with new jump
   // optimization, where jump-through-register instruction that usually
   // follows LUI/ORI pair is substituted with J/JAL, this constant equals

[paul.l..., 2016/01/11 22:34:57]

These comments about J/JAL should have been removed in
https://codereview.chromium.org/1419793014. Please remove them now.

[miran.karic, 2016/02/18 08:38:05]

Done.

-  // to 3 instructions (LUI+ORI+J/JAL/JR/JALR).
+// to 3 instructions (LUI+ORI+J/JAL/JR/JALR). On r6, 32bit constant is placed
+// in 2 instructions (LUI+JIC)
+#ifdef _MIPS_ARCH_MIPS32R6
+  static const int kInstructionsFor32BitConstant = 2;
+#else
   static const int kInstructionsFor32BitConstant = 3;

[paul.l..., 2016/01/11 22:34:57]

I _think_ this case of 3 was only useful when we had J/JAL optimization. I think
we should use 2 now everywhere. However, we must be certain that all tests work,
with and without snapshots on sim and board. It might be prudent to remove all
this cruft, and test/submit in a separate CL from this JIC work.

[miran.karic, 2016/02/18 08:38:05]

Done. New CL created.

+#endif
 
   // Distance between the instruction referring to the address of the call
   // target and the return address.
   static const int kCallTargetAddressOffset = 4 * kInstrSize;
 
   // Distance between start of patched debug break slot and the emitted address
   // to jump to.
   static const int kPatchDebugBreakSlotAddressOffset = 4 * kInstrSize;
 
   // Difference between address of current opcode and value read from pc
@@ skipping 540 matching lines @@
   // Check if an instruction is a branch of some kind.
   static bool IsBranch(Instr instr);
   static bool IsBc(Instr instr);
   static bool IsBzc(Instr instr);
   static bool IsBeq(Instr instr);
   static bool IsBne(Instr instr);
   static bool IsBeqzc(Instr instr);
   static bool IsBnezc(Instr instr);
   static bool IsBeqc(Instr instr);
   static bool IsBnec(Instr instr);
+  static bool IsJicOrJialc(Instr instr);
 
   static bool IsJump(Instr instr);
   static bool IsJ(Instr instr);
   static bool IsLui(Instr instr);
   static bool IsOri(Instr instr);
 
   static bool IsJal(Instr instr);
   static bool IsJr(Instr instr);
   static bool IsJalr(Instr instr);
 
@@ skipping 19 matching lines @@
   static uint32_t GetSaField(Instr instr);
   static uint32_t GetOpcodeField(Instr instr);
   static uint32_t GetFunction(Instr instr);
   static uint32_t GetFunctionField(Instr instr);
   static uint32_t GetImmediate16(Instr instr);
   static uint32_t GetLabelConst(Instr instr);
 
   static int32_t GetBranchOffset(Instr instr);
   static bool IsLw(Instr instr);
   static int16_t GetLwOffset(Instr instr);
+  static int16_t GetJicOrJialcOffset(Instr instr);
+  static int16_t GetLuiOffset(Instr instr);
   static Instr SetLwOffset(Instr instr, int16_t offset);
 
   static bool IsSw(Instr instr);
   static Instr SetSwOffset(Instr instr, int16_t offset);
   static bool IsAddImmediate(Instr instr);
   static Instr SetAddImmediateOffset(Instr instr, int16_t offset);
+  static uint32_t createTargetAddress(Instr instr_lui, Instr instr_jic);
+  static void unpackTargetAddress(uint32_t address, int16_t& lui_offset,
+                                  int16_t& jic_offset);
+  static void unpackTargetAddressUnsigned(uint32_t address,
+                                          uint32_t& lui_offset,
+                                          uint32_t& jic_offset);
 
   static bool IsAndImmediate(Instr instr);
   static bool IsEmittedConstant(Instr instr);
 
   void CheckTrampolinePool();
 
   void PatchConstantPoolAccessInstruction(int pc_offset, int offset,
                                           ConstantPoolEntry::Access access,
                                           ConstantPoolEntry::Type type) {
     // No embedded constant pool support.
@@ skipping 60 matching lines @@
     DCHECK(block_buffer_growth_);
     block_buffer_growth_ = false;
   }
 
   bool is_buffer_growth_blocked() const {
     return block_buffer_growth_;
   }
 
   inline void CheckTrampolinePoolQuick(int extra_instructions = 0);
 
+  inline void CheckBuffer();
+
  private:
   inline static void set_target_internal_reference_encoded_at(Address pc,
                                                               Address target);
 
   // Buffer size and constant pool distance are checked together at regular
   // intervals of kBufferCheckInterval emitted bytes.
   static const int kBufferCheckInterval = 1*KB/2;
 
   // Code generation.
   // The relocation writer's position is at least kGap bytes below the end of
@@ skipping 26 matching lines @@
   static const int kMaxRelocSize = RelocInfoWriter::kMaxSize;
   RelocInfoWriter reloc_info_writer;
 
   // The bound position, before this we cannot do instruction elimination.
   int last_bound_pos_;
 
   // Readable constants for compact branch handling in emit()
   enum class CompactBranchType : bool { NO = false, COMPACT_BRANCH = true };
 
   // Code emission.
-  inline void CheckBuffer();
   void GrowBuffer();
   inline void emit(Instr x,
                    CompactBranchType is_compact_branch = CompactBranchType::NO);
 
   // Instruction generation.
   // We have 3 different kind of encoding layout on MIPS.
   // However due to many different types of objects encoded in the same fields
   // we have quite a few aliases for each mode.
   // Using the same structure to refer to Register and FPURegister would spare a
   // few aliases, but mixing both does not look clean to me.
@@ skipping 121 matching lines @@
   };
 
   int32_t get_trampoline_entry(int32_t pos);
   int unbound_labels_count_;
   // If trampoline is emitted, generated code is becoming large. As this is
   // already a slow case which can possibly break our code generation for the
   // extreme case, we use this information to trigger different mode of
   // branch instruction generation, where we use jump instructions rather
   // than regular branch instructions.
   bool trampoline_emitted_;
+#ifdef _MIPS_ARCH_MIPS32R6
+  static const int kTrampolineSlotsSize = 2 * kInstrSize;
+#else
   static const int kTrampolineSlotsSize = 4 * kInstrSize;
+#endif
   static const int kMaxBranchOffset = (1 << (18 - 1)) - 1;
   static const int kMaxCompactBranchOffset = (1 << (28 - 1)) - 1;
   static const int kInvalidSlotPos = -1;
 
   // Internal reference positions, required for unbounded internal reference
   // labels.
   std::set<int> internal_reference_positions_;
 
   void EmittedCompactBranchInstruction() { prev_instr_compact_branch_ = true; }
   void ClearCompactBranchState() { prev_instr_compact_branch_ = false; }
@@ skipping 17 matching lines @@
  public:
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBuffer();
   }
 };
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_ARM_ASSEMBLER_MIPS_H_