Implements include/exclude register lists for translation.

src/IceTargetLoweringARM32.cpp

Index: src/IceTargetLoweringARM32.cpp
diff --git a/src/IceTargetLoweringARM32.cpp b/src/IceTargetLoweringARM32.cpp
index 08e26078de5390a26a9e7bf6705311e552420d5d..acbdba28565b1a9326af4c170225f3c9d3139476 100644
--- a/src/IceTargetLoweringARM32.cpp
+++ b/src/IceTargetLoweringARM32.cpp
@@ -50,8 +50,8 @@ createTargetHeaderLowering(::Ice::GlobalContext *Ctx) {
   return ::Ice::ARM32::TargetHeaderARM32::create(Ctx);
 }
 
-void staticInit(const ::Ice::ClFlags &Flags) {
-  ::Ice::ARM32::TargetARM32::staticInit(Flags);
+void staticInit(::Ice::GlobalContext *Ctx) {
+  ::Ice::ARM32::TargetARM32::staticInit(Ctx);
 }
 } // end of namespace ARM32
 
@@ -235,8 +235,8 @@ TargetARM32::TargetARM32(Cfg *Func)
     : TargetLowering(Func), NeedSandboxing(Ctx->getFlags().getUseSandboxing()),
       CPUFeatures(Func->getContext()->getFlags()) {}
 
-void TargetARM32::staticInit(const ClFlags &Flags) {
-  (void)Flags;
+void TargetARM32::staticInit(GlobalContext *Ctx) {
+
   // Limit this size (or do all bitsets need to be the same width)???
   llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector I64PairRegisters(RegARM32::Reg_NUM);
@@ -289,6 +289,18 @@ void TargetARM32::staticInit(const ClFlags &Flags) {
   TypeToRegisterSet[IceType_v8i16] = VectorRegisters;
   TypeToRegisterSet[IceType_v4i32] = VectorRegisters;
   TypeToRegisterSet[IceType_v4f32] = VectorRegisters;
+
+  filterTypeToRegisterSet(
+      Ctx, RegARM32::Reg_NUM, TypeToRegisterSet, RCARM32_NUM,
+      [](int32_t RegNum) -> IceString {
+        IceString Name = RegARM32::getRegName(RegNum);
+        constexpr const char RegSeparator[] = ", ";
+        for (size_t Pos = Name.find(RegSeparator); Pos != std::string::npos;
+             Pos = Name.find(RegSeparator)) {
+          Name.replace(Pos, llvm::array_lengthof(RegSeparator), ":");

[Jim Stichnoth, 2016/01/15 00:50:56]

I think something is wrong here, because it prints this:
  r0:1,r2:3,r4:5,r6:7
instead of:
  r0:r1,r2:r3,r4:r5,r6:r7

The previous time I checked (patchset 9 I believe), it printed this:
  r0:r1, r2:r3, r4:r5, r6:r7

[Karl, 2016/01/15 16:54:25]

Yep. My mistake. I tried to be too intelligent when switching to a constexpr
(from a std::string). Forgot to count the null character.

+        }
+        return Name;
+      });
 }
 
 namespace {
@@ -1832,7 +1844,7 @@ llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include,
                                                  RegSetMask Exclude) const {
   llvm::SmallBitVector Registers(RegARM32::Reg_NUM);
 
-  for (int i = 0; i < RegARM32::Reg_NUM; ++i) {
+  for (SizeT i = 0; i < RegARM32::Reg_NUM; ++i) {
     const auto &Entry = RegARM32::Table[i];
     if (Entry.Scratch && (Include & RegSet_CallerSave))
       Registers[i] = true;