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Side by Side Diff: src/IceTargetLoweringMIPS32.cpp

Issue 1571433004: Implements include/exclude register lists for translation. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nits. Created 4 years, 11 months ago
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1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===// 1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
(...skipping 27 matching lines...) Expand all
38 std::unique_ptr<::Ice::TargetDataLowering> 38 std::unique_ptr<::Ice::TargetDataLowering>
39 createTargetDataLowering(::Ice::GlobalContext *Ctx) { 39 createTargetDataLowering(::Ice::GlobalContext *Ctx) {
40 return ::Ice::MIPS32::TargetDataMIPS32::create(Ctx); 40 return ::Ice::MIPS32::TargetDataMIPS32::create(Ctx);
41 } 41 }
42 42
43 std::unique_ptr<::Ice::TargetHeaderLowering> 43 std::unique_ptr<::Ice::TargetHeaderLowering>
44 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) { 44 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) {
45 return ::Ice::MIPS32::TargetHeaderMIPS32::create(Ctx); 45 return ::Ice::MIPS32::TargetHeaderMIPS32::create(Ctx);
46 } 46 }
47 47
48 void staticInit(const ::Ice::ClFlags &Flags) { 48 void staticInit(::Ice::GlobalContext *Ctx) {
49 ::Ice::MIPS32::TargetMIPS32::staticInit(Flags); 49 ::Ice::MIPS32::TargetMIPS32::staticInit(Ctx);
50 } 50 }
51 } // end of namespace MIPS32 51 } // end of namespace MIPS32
52 52
53 namespace Ice { 53 namespace Ice {
54 namespace MIPS32 { 54 namespace MIPS32 {
55 55
56 using llvm::isInt; 56 using llvm::isInt;
57 57
58 namespace { 58 namespace {
59 59
60 // The maximum number of arguments to pass in GPR registers. 60 // The maximum number of arguments to pass in GPR registers.
61 constexpr uint32_t MIPS32_MAX_GPR_ARG = 4; 61 constexpr uint32_t MIPS32_MAX_GPR_ARG = 4;
62 62
63 } // end of anonymous namespace 63 } // end of anonymous namespace
64 64
65 TargetMIPS32::TargetMIPS32(Cfg *Func) : TargetLowering(Func) {} 65 TargetMIPS32::TargetMIPS32(Cfg *Func) : TargetLowering(Func) {}
66 66
67 void TargetMIPS32::staticInit(const ClFlags &Flags) { 67 void TargetMIPS32::staticInit(GlobalContext *Ctx) {
68 (void)Flags; 68 (void)Ctx;
69 llvm::SmallBitVector IntegerRegisters(RegMIPS32::Reg_NUM); 69 llvm::SmallBitVector IntegerRegisters(RegMIPS32::Reg_NUM);
70 llvm::SmallBitVector I64PairRegisters(RegMIPS32::Reg_NUM); 70 llvm::SmallBitVector I64PairRegisters(RegMIPS32::Reg_NUM);
71 llvm::SmallBitVector Float32Registers(RegMIPS32::Reg_NUM); 71 llvm::SmallBitVector Float32Registers(RegMIPS32::Reg_NUM);
72 llvm::SmallBitVector Float64Registers(RegMIPS32::Reg_NUM); 72 llvm::SmallBitVector Float64Registers(RegMIPS32::Reg_NUM);
73 llvm::SmallBitVector VectorRegisters(RegMIPS32::Reg_NUM); 73 llvm::SmallBitVector VectorRegisters(RegMIPS32::Reg_NUM);
74 llvm::SmallBitVector InvalidRegisters(RegMIPS32::Reg_NUM); 74 llvm::SmallBitVector InvalidRegisters(RegMIPS32::Reg_NUM);
75 ScratchRegs.resize(RegMIPS32::Reg_NUM); 75 ScratchRegs.resize(RegMIPS32::Reg_NUM);
76 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ 76 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
77 isI64Pair, isFP32, isFP64, isVec128, alias_init) \ 77 isI64Pair, isFP32, isFP64, isVec128, alias_init) \
78 IntegerRegisters[RegMIPS32::val] = isInt; \ 78 IntegerRegisters[RegMIPS32::val] = isInt; \
(...skipping 1022 matching lines...) Expand 10 before | Expand all | Expand 10 after
1101 Str << "\t.set\t" 1101 Str << "\t.set\t"
1102 << "nomips16\n"; 1102 << "nomips16\n";
1103 } 1103 }
1104 1104
1105 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[IceType_NUM]; 1105 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[IceType_NUM];
1106 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; 1106 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
1107 llvm::SmallBitVector TargetMIPS32::ScratchRegs; 1107 llvm::SmallBitVector TargetMIPS32::ScratchRegs;
1108 1108
1109 } // end of namespace MIPS32 1109 } // end of namespace MIPS32
1110 } // end of namespace Ice 1110 } // end of namespace Ice
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