Implements include/exclude register lists for translation.

src/IceRegistersARM32.h

 //===- subzero/src/IceRegistersARM32.h - Register information ---*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 128 matching lines @@
   {                                                                            \
     name, encode, cc_arg, scratch, preserved, stackptr, frameptr, isGPR,       \
         isInt, isI64Pair, isFP32, isFP64, isVec128,                            \
         (SizeOf alias_init).size(), alias_init                                 \
   }                                                                            \
   ,
       REGARM32_TABLE
 #undef X
   };
 
+  enum RegClass {

[Jim Stichnoth, 2016/01/13 16:24:54]

FWIW, there is already Ice::RegClass defined in IceOperand.h.

That got me thinking.  There is probably a reasonable way to leverage that
existing register class infrastructure to accomplish this without needing to add
these new data structures.  I'll have to think about that a bit more.

[Karl, 2016/01/14 18:27:19]

Changed to use TypeToRegisterSet vectors for this concept, removing the need for
duplicating register classes.

+    RegClass_GP,
+    RegClass_GPPair,
+    RegClass_S,
+    RegClass_D,
+    RegClass_Q,
+    RegClass_Other,
+    // Defines the number of RegClass'es
+    Num_RegClasses

[Jim Stichnoth, 2016/01/13 16:24:54]

Usually this dummy value is named something like RegClass_NUM (to keep the same
prefix on all enum values).

[Karl, 2016/01/14 18:27:19]

Done.

+  };
+
   static inline void assertRegisterDefined(int32_t RegNum) {
     (void)RegNum;
     assert(RegNum >= 0);
     assert(RegNum < Reg_NUM);
   }
 
+  static RegClass getRegClass(int32_t RegNum) {

[Jim Stichnoth, 2016/01/13 16:24:54]

I'm not sure why some of these functions are "static" and others "static
inline".

Probably "class RegARM32" should be changed to "namespace RegARM32", then all of
these would just be "inline".

[Karl, 2016/01/14 18:27:19]

The inline's are removed. I left removing class RegARM32 to a separate CL (and
added a TODO).

+    assert(RegNum >= 0);
+    assert(RegNum < Reg_NUM);
+    if (Table[RegNum].IsGPR)
+      return RegClass_GP;
+    if (Table[RegNum].IsI64Pair)
+      return RegClass_GPPair;
+    if (Table[RegNum].IsFP32)
+      return RegClass_S;
+    if (Table[RegNum].IsFP64)
+      return RegClass_D;
+    if (Table[RegNum].IsVec128)
+      return RegClass_Q;
+    return RegClass_Other;
+  }
+
   static inline bool isGPRegister(int32_t RegNum) {
     assertRegisterDefined(RegNum);
     return Table[RegNum].IsGPR;
   }
 
   static constexpr SizeT getNumGPRegs() {
     return 0
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
           isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   +(isGPR)
@@ skipping 103 matching lines @@
   }
 };
 
 // Extend enum RegClass with ARM32-specific register classes (if any).
 enum RegClassARM32 : uint8_t { RCARM32_NUM = RC_Target };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEREGISTERSARM32_H