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Side by Side Diff: src/IceTargetLoweringX86BaseImpl.h

Issue 1571433004: Implements include/exclude register lists for translation. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nits. Created 4 years, 11 months ago
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1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==// 1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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317 if (Func->getContext()->getFlags().getTargetInstructionSet() != 317 if (Func->getContext()->getFlags().getTargetInstructionSet() !=
318 TargetInstructionSet::BaseInstructionSet) { 318 TargetInstructionSet::BaseInstructionSet) {
319 InstructionSet = static_cast<InstructionSetEnum>( 319 InstructionSet = static_cast<InstructionSetEnum>(
320 (Func->getContext()->getFlags().getTargetInstructionSet() - 320 (Func->getContext()->getFlags().getTargetInstructionSet() -
321 TargetInstructionSet::X86InstructionSet_Begin) + 321 TargetInstructionSet::X86InstructionSet_Begin) +
322 Traits::InstructionSet::Begin); 322 Traits::InstructionSet::Begin);
323 } 323 }
324 } 324 }
325 325
326 template <typename TraitsType> 326 template <typename TraitsType>
327 void TargetX86Base<TraitsType>::staticInit(const ClFlags &Flags) { 327 void TargetX86Base<TraitsType>::staticInit(GlobalContext *Ctx) {
328 Traits::initRegisterSet(Flags, &TypeToRegisterSet, &RegisterAliases, 328 Traits::initRegisterSet(Ctx->getFlags(), &TypeToRegisterSet, &RegisterAliases,
329 &ScratchRegs); 329 &ScratchRegs);
330 filterTypeToRegisterSet(Ctx, Traits::RegisterSet::Reg_NUM,
331 TypeToRegisterSet.data(), TypeToRegisterSet.size(),
332 Traits::getRegName);
330 PcRelFixup = Traits::FK_PcRel; 333 PcRelFixup = Traits::FK_PcRel;
331 AbsFixup = Flags.getUseNonsfi() ? Traits::FK_Gotoff : Traits::FK_Abs; 334 AbsFixup =
335 Ctx->getFlags().getUseNonsfi() ? Traits::FK_Gotoff : Traits::FK_Abs;
332 } 336 }
333 337
334 template <typename TraitsType> void TargetX86Base<TraitsType>::translateO2() { 338 template <typename TraitsType> void TargetX86Base<TraitsType>::translateO2() {
335 TimerMarker T(TimerStack::TT_O2, Func); 339 TimerMarker T(TimerStack::TT_O2, Func);
336 340
337 if (!Traits::Is64Bit && Func->getContext()->getFlags().getUseNonsfi()) { 341 if (!Traits::Is64Bit && Func->getContext()->getFlags().getUseNonsfi()) {
338 GotVar = Func->makeVariable(IceType_i32); 342 GotVar = Func->makeVariable(IceType_i32);
339 } 343 }
340 344
341 if (NeedSandboxing) { 345 if (NeedSandboxing) {
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6616 Func, MemOperand->getType(), RegTemp, nullptr, MemOperand->getIndex(), 6620 Func, MemOperand->getType(), RegTemp, nullptr, MemOperand->getIndex(),
6617 MemOperand->getShift(), MemOperand->getSegmentRegister()); 6621 MemOperand->getShift(), MemOperand->getSegmentRegister());
6618 return NewMemOperand; 6622 return NewMemOperand;
6619 } 6623 }
6620 } 6624 }
6621 } 6625 }
6622 } // end of namespace X86NAMESPACE 6626 } // end of namespace X86NAMESPACE
6623 } // end of namespace Ice 6627 } // end of namespace Ice
6624 6628
6625 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H 6629 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H
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