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1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===// | 1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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38 std::unique_ptr<::Ice::TargetDataLowering> | 38 std::unique_ptr<::Ice::TargetDataLowering> |
39 createTargetDataLowering(::Ice::GlobalContext *Ctx) { | 39 createTargetDataLowering(::Ice::GlobalContext *Ctx) { |
40 return ::Ice::MIPS32::TargetDataMIPS32::create(Ctx); | 40 return ::Ice::MIPS32::TargetDataMIPS32::create(Ctx); |
41 } | 41 } |
42 | 42 |
43 std::unique_ptr<::Ice::TargetHeaderLowering> | 43 std::unique_ptr<::Ice::TargetHeaderLowering> |
44 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) { | 44 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) { |
45 return ::Ice::MIPS32::TargetHeaderMIPS32::create(Ctx); | 45 return ::Ice::MIPS32::TargetHeaderMIPS32::create(Ctx); |
46 } | 46 } |
47 | 47 |
48 void staticInit(const ::Ice::ClFlags &Flags) { | 48 void staticInit(::Ice::GlobalContext *Ctx) { |
49 ::Ice::MIPS32::TargetMIPS32::staticInit(Flags); | 49 ::Ice::MIPS32::TargetMIPS32::staticInit(Ctx); |
50 } | 50 } |
51 } // end of namespace MIPS32 | 51 } // end of namespace MIPS32 |
52 | 52 |
53 namespace Ice { | 53 namespace Ice { |
54 namespace MIPS32 { | 54 namespace MIPS32 { |
55 | 55 |
56 using llvm::isInt; | 56 using llvm::isInt; |
57 | 57 |
58 namespace { | 58 namespace { |
59 | 59 |
60 // The maximum number of arguments to pass in GPR registers. | 60 // The maximum number of arguments to pass in GPR registers. |
61 constexpr uint32_t MIPS32_MAX_GPR_ARG = 4; | 61 constexpr uint32_t MIPS32_MAX_GPR_ARG = 4; |
62 | 62 |
63 } // end of anonymous namespace | 63 } // end of anonymous namespace |
64 | 64 |
65 TargetMIPS32::TargetMIPS32(Cfg *Func) : TargetLowering(Func) {} | 65 TargetMIPS32::TargetMIPS32(Cfg *Func) : TargetLowering(Func) {} |
66 | 66 |
67 void TargetMIPS32::staticInit(const ClFlags &Flags) { | 67 void TargetMIPS32::staticInit(GlobalContext *Ctx) { |
68 (void)Flags; | 68 (void)Ctx; |
69 llvm::SmallBitVector IntegerRegisters(RegMIPS32::Reg_NUM); | 69 llvm::SmallBitVector IntegerRegisters(RegMIPS32::Reg_NUM); |
70 llvm::SmallBitVector I64PairRegisters(RegMIPS32::Reg_NUM); | 70 llvm::SmallBitVector I64PairRegisters(RegMIPS32::Reg_NUM); |
71 llvm::SmallBitVector Float32Registers(RegMIPS32::Reg_NUM); | 71 llvm::SmallBitVector Float32Registers(RegMIPS32::Reg_NUM); |
72 llvm::SmallBitVector Float64Registers(RegMIPS32::Reg_NUM); | 72 llvm::SmallBitVector Float64Registers(RegMIPS32::Reg_NUM); |
73 llvm::SmallBitVector VectorRegisters(RegMIPS32::Reg_NUM); | 73 llvm::SmallBitVector VectorRegisters(RegMIPS32::Reg_NUM); |
74 llvm::SmallBitVector InvalidRegisters(RegMIPS32::Reg_NUM); | 74 llvm::SmallBitVector InvalidRegisters(RegMIPS32::Reg_NUM); |
75 ScratchRegs.resize(RegMIPS32::Reg_NUM); | 75 ScratchRegs.resize(RegMIPS32::Reg_NUM); |
76 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ | 76 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ |
77 isI64Pair, isFP32, isFP64, isVec128, alias_init) \ | 77 isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
78 IntegerRegisters[RegMIPS32::val] = isInt; \ | 78 IntegerRegisters[RegMIPS32::val] = isInt; \ |
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99 TypeToRegisterSet[IceType_i64] = IntegerRegisters; | 99 TypeToRegisterSet[IceType_i64] = IntegerRegisters; |
100 TypeToRegisterSet[IceType_f32] = Float32Registers; | 100 TypeToRegisterSet[IceType_f32] = Float32Registers; |
101 TypeToRegisterSet[IceType_f64] = Float64Registers; | 101 TypeToRegisterSet[IceType_f64] = Float64Registers; |
102 TypeToRegisterSet[IceType_v4i1] = VectorRegisters; | 102 TypeToRegisterSet[IceType_v4i1] = VectorRegisters; |
103 TypeToRegisterSet[IceType_v8i1] = VectorRegisters; | 103 TypeToRegisterSet[IceType_v8i1] = VectorRegisters; |
104 TypeToRegisterSet[IceType_v16i1] = VectorRegisters; | 104 TypeToRegisterSet[IceType_v16i1] = VectorRegisters; |
105 TypeToRegisterSet[IceType_v16i8] = VectorRegisters; | 105 TypeToRegisterSet[IceType_v16i8] = VectorRegisters; |
106 TypeToRegisterSet[IceType_v8i16] = VectorRegisters; | 106 TypeToRegisterSet[IceType_v8i16] = VectorRegisters; |
107 TypeToRegisterSet[IceType_v4i32] = VectorRegisters; | 107 TypeToRegisterSet[IceType_v4i32] = VectorRegisters; |
108 TypeToRegisterSet[IceType_v4f32] = VectorRegisters; | 108 TypeToRegisterSet[IceType_v4f32] = VectorRegisters; |
| 109 |
| 110 filterTypeToRegisterSet(Ctx, RegMIPS32::Reg_NUM, TypeToRegisterSet, |
| 111 RCMIPS32_NUM, [](int32_t RegNum) -> IceString { |
| 112 return RegMIPS32::getRegName(RegNum); |
| 113 }); |
109 } | 114 } |
110 | 115 |
111 void TargetMIPS32::translateO2() { | 116 void TargetMIPS32::translateO2() { |
112 TimerMarker T(TimerStack::TT_O2, Func); | 117 TimerMarker T(TimerStack::TT_O2, Func); |
113 | 118 |
114 // TODO(stichnot): share passes with X86? | 119 // TODO(stichnot): share passes with X86? |
115 // https://code.google.com/p/nativeclient/issues/detail?id=4094 | 120 // https://code.google.com/p/nativeclient/issues/detail?id=4094 |
116 genTargetHelperCalls(); | 121 genTargetHelperCalls(); |
117 | 122 |
118 // Merge Alloca instructions, and lay out the stack. | 123 // Merge Alloca instructions, and lay out the stack. |
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255 } | 260 } |
256 } | 261 } |
257 | 262 |
258 bool TargetMIPS32::doBranchOpt(Inst *I, const CfgNode *NextNode) { | 263 bool TargetMIPS32::doBranchOpt(Inst *I, const CfgNode *NextNode) { |
259 (void)I; | 264 (void)I; |
260 (void)NextNode; | 265 (void)NextNode; |
261 UnimplementedError(Func->getContext()->getFlags()); | 266 UnimplementedError(Func->getContext()->getFlags()); |
262 return false; | 267 return false; |
263 } | 268 } |
264 | 269 |
265 IceString TargetMIPS32::getRegName(SizeT RegNum, Type Ty) const { | 270 namespace { |
266 assert(RegNum < RegMIPS32::Reg_NUM); | 271 |
267 (void)Ty; | 272 const char *RegNames[RegMIPS32::Reg_NUM] = { |
268 static const char *RegNames[] = { | |
269 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ | 273 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ |
270 isI64Pair, isFP32, isFP64, isVec128, alias_init) \ | 274 isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
271 name, | 275 name, |
272 REGMIPS32_TABLE | 276 REGMIPS32_TABLE |
273 #undef X | 277 #undef X |
274 }; | 278 }; |
| 279 |
| 280 } // end of anonymous namespace |
| 281 |
| 282 const char *RegMIPS32::getRegName(int32_t RegNum) { |
| 283 assert(RegNum < RegMIPS32::Reg_NUM); |
275 return RegNames[RegNum]; | 284 return RegNames[RegNum]; |
276 } | 285 } |
277 | 286 |
| 287 IceString TargetMIPS32::getRegName(SizeT RegNum, Type Ty) const { |
| 288 (void)Ty; |
| 289 return RegMIPS32::getRegName(RegNum); |
| 290 } |
| 291 |
278 Variable *TargetMIPS32::getPhysicalRegister(SizeT RegNum, Type Ty) { | 292 Variable *TargetMIPS32::getPhysicalRegister(SizeT RegNum, Type Ty) { |
279 if (Ty == IceType_void) | 293 if (Ty == IceType_void) |
280 Ty = IceType_i32; | 294 Ty = IceType_i32; |
281 if (PhysicalRegisters[Ty].empty()) | 295 if (PhysicalRegisters[Ty].empty()) |
282 PhysicalRegisters[Ty].resize(RegMIPS32::Reg_NUM); | 296 PhysicalRegisters[Ty].resize(RegMIPS32::Reg_NUM); |
283 assert(RegNum < PhysicalRegisters[Ty].size()); | 297 assert(RegNum < PhysicalRegisters[Ty].size()); |
284 Variable *Reg = PhysicalRegisters[Ty][RegNum]; | 298 Variable *Reg = PhysicalRegisters[Ty][RegNum]; |
285 if (Reg == nullptr) { | 299 if (Reg == nullptr) { |
286 Reg = Func->makeVariable(Ty); | 300 Reg = Func->makeVariable(Ty); |
287 Reg->setRegNum(RegNum); | 301 Reg->setRegNum(RegNum); |
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1101 Str << "\t.set\t" | 1115 Str << "\t.set\t" |
1102 << "nomips16\n"; | 1116 << "nomips16\n"; |
1103 } | 1117 } |
1104 | 1118 |
1105 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[IceType_NUM]; | 1119 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[IceType_NUM]; |
1106 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; | 1120 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; |
1107 llvm::SmallBitVector TargetMIPS32::ScratchRegs; | 1121 llvm::SmallBitVector TargetMIPS32::ScratchRegs; |
1108 | 1122 |
1109 } // end of namespace MIPS32 | 1123 } // end of namespace MIPS32 |
1110 } // end of namespace Ice | 1124 } // end of namespace Ice |
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