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1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// | 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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43 std::unique_ptr<::Ice::TargetDataLowering> | 43 std::unique_ptr<::Ice::TargetDataLowering> |
44 createTargetDataLowering(::Ice::GlobalContext *Ctx) { | 44 createTargetDataLowering(::Ice::GlobalContext *Ctx) { |
45 return ::Ice::ARM32::TargetDataARM32::create(Ctx); | 45 return ::Ice::ARM32::TargetDataARM32::create(Ctx); |
46 } | 46 } |
47 | 47 |
48 std::unique_ptr<::Ice::TargetHeaderLowering> | 48 std::unique_ptr<::Ice::TargetHeaderLowering> |
49 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) { | 49 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) { |
50 return ::Ice::ARM32::TargetHeaderARM32::create(Ctx); | 50 return ::Ice::ARM32::TargetHeaderARM32::create(Ctx); |
51 } | 51 } |
52 | 52 |
53 void staticInit(const ::Ice::ClFlags &Flags) { | 53 void staticInit(::Ice::GlobalContext *Ctx) { |
54 ::Ice::ARM32::TargetARM32::staticInit(Flags); | 54 ::Ice::ARM32::TargetARM32::staticInit(Ctx); |
55 } | 55 } |
56 | 56 |
57 } // end of namespace ARM32 | 57 } // end of namespace ARM32 |
58 | 58 |
59 namespace Ice { | 59 namespace Ice { |
60 namespace ARM32 { | 60 namespace ARM32 { |
61 | 61 |
62 namespace { | 62 namespace { |
63 | 63 |
64 /// SizeOf is used to obtain the size of an initializer list as a constexpr | 64 /// SizeOf is used to obtain the size of an initializer list as a constexpr |
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270 REGARM32_VEC128_TABLE | 270 REGARM32_VEC128_TABLE |
271 #undef X | 271 #undef X |
272 ; | 272 ; |
273 std::array<uint32_t, NumVec128Args> Vec128ArgInitializer; | 273 std::array<uint32_t, NumVec128Args> Vec128ArgInitializer; |
274 } // end of anonymous namespace | 274 } // end of anonymous namespace |
275 | 275 |
276 TargetARM32::TargetARM32(Cfg *Func) | 276 TargetARM32::TargetARM32(Cfg *Func) |
277 : TargetLowering(Func), NeedSandboxing(Ctx->getFlags().getUseSandboxing()), | 277 : TargetLowering(Func), NeedSandboxing(Ctx->getFlags().getUseSandboxing()), |
278 CPUFeatures(Func->getContext()->getFlags()) {} | 278 CPUFeatures(Func->getContext()->getFlags()) {} |
279 | 279 |
280 void TargetARM32::staticInit(const ClFlags &Flags) { | 280 void TargetARM32::staticInit(GlobalContext *Ctx) { |
281 (void)Flags; | 281 |
282 // Limit this size (or do all bitsets need to be the same width)??? | 282 // Limit this size (or do all bitsets need to be the same width)??? |
283 llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM); | 283 llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM); |
284 llvm::SmallBitVector I64PairRegisters(RegARM32::Reg_NUM); | 284 llvm::SmallBitVector I64PairRegisters(RegARM32::Reg_NUM); |
285 llvm::SmallBitVector Float32Registers(RegARM32::Reg_NUM); | 285 llvm::SmallBitVector Float32Registers(RegARM32::Reg_NUM); |
286 llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM); | 286 llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM); |
287 llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM); | 287 llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM); |
288 llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM); | 288 llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM); |
289 ScratchRegs.resize(RegARM32::Reg_NUM); | 289 ScratchRegs.resize(RegARM32::Reg_NUM); |
290 for (int i = 0; i < RegARM32::Reg_NUM; ++i) { | 290 for (int i = 0; i < RegARM32::Reg_NUM; ++i) { |
291 const auto &Entry = RegARM32::RegTable[i]; | 291 const auto &Entry = RegARM32::RegTable[i]; |
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324 TypeToRegisterSet[IceType_i64] = I64PairRegisters; | 324 TypeToRegisterSet[IceType_i64] = I64PairRegisters; |
325 TypeToRegisterSet[IceType_f32] = Float32Registers; | 325 TypeToRegisterSet[IceType_f32] = Float32Registers; |
326 TypeToRegisterSet[IceType_f64] = Float64Registers; | 326 TypeToRegisterSet[IceType_f64] = Float64Registers; |
327 TypeToRegisterSet[IceType_v4i1] = VectorRegisters; | 327 TypeToRegisterSet[IceType_v4i1] = VectorRegisters; |
328 TypeToRegisterSet[IceType_v8i1] = VectorRegisters; | 328 TypeToRegisterSet[IceType_v8i1] = VectorRegisters; |
329 TypeToRegisterSet[IceType_v16i1] = VectorRegisters; | 329 TypeToRegisterSet[IceType_v16i1] = VectorRegisters; |
330 TypeToRegisterSet[IceType_v16i8] = VectorRegisters; | 330 TypeToRegisterSet[IceType_v16i8] = VectorRegisters; |
331 TypeToRegisterSet[IceType_v8i16] = VectorRegisters; | 331 TypeToRegisterSet[IceType_v8i16] = VectorRegisters; |
332 TypeToRegisterSet[IceType_v4i32] = VectorRegisters; | 332 TypeToRegisterSet[IceType_v4i32] = VectorRegisters; |
333 TypeToRegisterSet[IceType_v4f32] = VectorRegisters; | 333 TypeToRegisterSet[IceType_v4f32] = VectorRegisters; |
| 334 |
| 335 filterTypeToRegisterSet( |
| 336 Ctx, RegARM32::Reg_NUM, TypeToRegisterSet, RegARM32::RCARM32_NUM, |
| 337 [](int32_t RegNum) -> IceString { |
| 338 IceString Name = RegARM32::getRegName(RegNum); |
| 339 constexpr const char RegSeparator[] = ", "; |
| 340 constexpr size_t RegSeparatorWidth = |
| 341 llvm::array_lengthof(RegSeparator) - 1; |
| 342 for (size_t Pos = Name.find(RegSeparator); Pos != std::string::npos; |
| 343 Pos = Name.find(RegSeparator)) { |
| 344 Name.replace(Pos, RegSeparatorWidth, ":"); |
| 345 } |
| 346 return Name; |
| 347 }); |
334 } | 348 } |
335 | 349 |
336 namespace { | 350 namespace { |
337 void copyRegAllocFromInfWeightVariable64On32(const VarList &Vars) { | 351 void copyRegAllocFromInfWeightVariable64On32(const VarList &Vars) { |
338 for (Variable *Var : Vars) { | 352 for (Variable *Var : Vars) { |
339 auto *Var64 = llvm::dyn_cast<Variable64On32>(Var); | 353 auto *Var64 = llvm::dyn_cast<Variable64On32>(Var); |
340 if (!Var64) { | 354 if (!Var64) { |
341 // This is not the variable we are looking for. | 355 // This is not the variable we are looking for. |
342 continue; | 356 continue; |
343 } | 357 } |
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1867 } | 1881 } |
1868 } | 1882 } |
1869 llvm::report_fatal_error("Unsupported operand type"); | 1883 llvm::report_fatal_error("Unsupported operand type"); |
1870 return nullptr; | 1884 return nullptr; |
1871 } | 1885 } |
1872 | 1886 |
1873 llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include, | 1887 llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include, |
1874 RegSetMask Exclude) const { | 1888 RegSetMask Exclude) const { |
1875 llvm::SmallBitVector Registers(RegARM32::Reg_NUM); | 1889 llvm::SmallBitVector Registers(RegARM32::Reg_NUM); |
1876 | 1890 |
1877 for (int i = 0; i < RegARM32::Reg_NUM; ++i) { | 1891 for (int32_t i = 0; i < RegARM32::Reg_NUM; ++i) { |
1878 const auto &Entry = RegARM32::RegTable[i]; | 1892 const auto &Entry = RegARM32::RegTable[i]; |
1879 if (Entry.Scratch && (Include & RegSet_CallerSave)) | 1893 if (Entry.Scratch && (Include & RegSet_CallerSave)) |
1880 Registers[i] = true; | 1894 Registers[i] = true; |
1881 if (Entry.Preserved && (Include & RegSet_CalleeSave)) | 1895 if (Entry.Preserved && (Include & RegSet_CalleeSave)) |
1882 Registers[i] = true; | 1896 Registers[i] = true; |
1883 if (Entry.StackPtr && (Include & RegSet_StackPointer)) | 1897 if (Entry.StackPtr && (Include & RegSet_StackPointer)) |
1884 Registers[i] = true; | 1898 Registers[i] = true; |
1885 if (Entry.FramePtr && (Include & RegSet_FramePointer)) | 1899 if (Entry.FramePtr && (Include & RegSet_FramePointer)) |
1886 Registers[i] = true; | 1900 Registers[i] = true; |
1887 if (Entry.Scratch && (Exclude & RegSet_CallerSave)) | 1901 if (Entry.Scratch && (Exclude & RegSet_CallerSave)) |
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6491 // However, for compatibility with current NaCl LLVM, don't claim that. | 6505 // However, for compatibility with current NaCl LLVM, don't claim that. |
6492 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; | 6506 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; |
6493 } | 6507 } |
6494 | 6508 |
6495 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM]; | 6509 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[IceType_NUM]; |
6496 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; | 6510 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; |
6497 llvm::SmallBitVector TargetARM32::ScratchRegs; | 6511 llvm::SmallBitVector TargetARM32::ScratchRegs; |
6498 | 6512 |
6499 } // end of namespace ARM32 | 6513 } // end of namespace ARM32 |
6500 } // end of namespace Ice | 6514 } // end of namespace Ice |
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