Implements include/exclude register lists for translation.

tests_lit/assembler/arm32/vadd.ll

 ; Show that we know how to translate vadd.
 
-; NOTE: We use -O2 to get rid of memory stores.
+; NOTE: Restricts S and D registers to ones that will better test S/D
+; register encodings.
 
 ; REQUIRES: allow_dump
 
 ; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
+; RUN:   -use-registers s20,s22,d20,d22 \
 ; RUN:   | FileCheck %s --check-prefix=ASM
 
 ; Show bytes in assembled standalone code.
 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
+; RUN:   --args -Om1 \
+; RUN:   -use-registers s20,s22,d20,d22 \
+; RUN:   | FileCheck %s --check-prefix=DIS
 
 ; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
+; RUN:   -use-registers s20,s22,d20,d22 \
 ; RUN:   | FileCheck %s --check-prefix=IASM
 
 ; Show bytes in assembled integrated code.
 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
+; RUN:   --args -Om1 \
+; RUN:   -use-registers s20,s22,d20,d22 \
+; RUN:   | FileCheck %s --check-prefix=DIS
 
 define internal float @testVaddFloat(float %v1, float %v2) {
 ; ASM-LABEL: testVaddFloat:
 ; DIS-LABEL: 00000000 <testVaddFloat>:
 ; IASM-LABEL: testVaddFloat:
 
 entry:
 ; ASM-NEXT: .LtestVaddFloat$entry:
 ; IASM-NEXT: .LtestVaddFloat$entry:
 
+; ASM-NEXT:     vpush   {s20}
+; DIS-NEXT:    0:       ed2daa01
+; IASM-NEXT:    .byte 0x1
+; IASM-NEXT:    .byte 0xaa
+; IASM-NEXT:    .byte 0x2d
+; IASM-NEXT:    .byte 0xed
+
+; ASM-NEXT:     vpush   {s22}
+; DIS-NEXT:    4:       ed2dba01
+; IASM-NEXT:    .byte 0x1
+; IASM-NEXT:    .byte 0xba
+; IASM-NEXT:    .byte 0x2d
+; IASM-NEXT:    .byte 0xed
+
+; ASM-NEXT:     sub     sp, sp, #12
+; DIS-NEXT:    8:       e24dd00c
+; IASM-NEXT:    .byte 0xc
+; IASM-NEXT:    .byte 0xd0
+; IASM-NEXT:    .byte 0x4d
+; IASM-NEXT:    .byte 0xe2
+
+; ASM-NEXT:     vstr    s0, [sp, #8]
+; ASM-NEXT:     # [sp, #8] = def.pseudo 

[Jim Stichnoth, 2016/01/10 16:51:26]

Trailing whitespace here and 3 other places.

Actually it turns out that's just the tip of the iceberg:

  git grep ' $'

Fix the new ones here, and the rest in a separate CL.

[Karl, 2016/01/12 23:44:05]

Acknowledged.

+; DIS-NEXT:    c:       ed8d0a02
+; IASM-NEXT:    vstr    s0, [sp, #8]
+
+; ASM-NEXT:     vstr    s1, [sp, #4]
+; ASM-NEXT:    # [sp, #4] = def.pseudo 
+; DIS-NEXT:   10:       edcd0a01
+; IASM-NEXT:    vstr    s1, [sp, #4]
+
   %res = fadd float %v1, %v2
 
-; ASM-NEXT:     vadd.f32        s0, s0, s1
-; DIS-NEXT:    0:       ee300a20
-; IASM-NEXT:    .byte 0x20
-; IASM-NEXT:    .byte 0xa
-; IASM-NEXT:    .byte 0x30
-; IASM-NEXT:    .byte 0xee
+; ASM-NEXT:     vldr    s20, [sp, #8]
+; DIS-NEXT:   14:       ed9daa02

[Jim Stichnoth, 2016/01/10 16:51:26]

untabify

[Karl, 2016/01/14 18:27:19]

Done.

+; IASM-NEXT:    vldr    s20, [sp, #8]
+
+; ASM-NEXT:     vldr    s22, [sp, #4]
+; DIS-NEXT:   18:       ed9dba01
+; IASM-NEXT:    vldr    s22, [sp, #4]
+
+; ASM-NEXT:     vadd.f32        s20, s20, s22
+; DIS-NEXT:   1c:       ee3aaa0b
+; IASM-NEXT:    .byte 0xb
+; IASM-NEXT:    .byte 0xaa
+; IASM-NEXT:    .byte 0x3a
+; IASM-NEXT:    .byte 0xee
 
   ret float %res
 }
 
 define internal double @testVaddDouble(double %v1, double %v2) {
 ; ASM-LABEL: testVaddDouble:
-; DIS-LABEL: 00000010 <testVaddDouble>:
-; IASM-LABEL: testVaddDouble:
+; DIS-LABEL: 00000040 <testVaddDouble>:
+; IASM-LABEL: .LtestVaddDouble$entry:
 
 entry:
 ; ASM-NEXT: .LtestVaddDouble$entry:
-; IASM-NEXT: .LtestVaddDouble$entry:
+
+; ASM-NEXT:     sub     sp, sp, #24
+; DIS-NEXT:   40:       e24dd018
+; IASM-NEXT:    .byte 0x18
+; IASM-NEXT:    .byte 0xd0
+; IASM-NEXT:    .byte 0x4d
+; IASM-NEXT:    .byte 0xe2
+
+; ASM-NEXT:     vstr    d0, [sp, #16]
+; ASM-NEXT:     # [sp, #16] = def.pseudo 
+; DIS-NEXT:   44:       ed8d0b04
+; IASM-NEXT:    vstr    d0, [sp, #16]
+
+; ASM-NEXT:     vstr    d1, [sp, #8]
+; ASM-NEXT:     # [sp, #8] = def.pseudo 
+; DIS-NEXT:   48:       ed8d1b02
+; IASM-NEXT:    vstr    d1, [sp, #8]
 
   %res = fadd double %v1, %v2
 
-; ASM-NEXT:     vadd.f64        d0, d0, d1
-; DIS-NEXT:   10:       ee300b01
-; IASM-NEXT:    .byte 0x1
-; IASM-NEXT:    .byte 0xb
-; IASM-NEXT:    .byte 0x30
-; IASM-NEXT:    .byte 0xee
+; ASM-NEXT:     vldr    d22, [sp, #16]
+; DIS-NEXT:   4c:       eddd6b04
+; IASM-NEXT:    vldr    d22, [sp, #16]
+
+; ASM-NEXT:     vldr    d20, [sp, #8]
+; DIS-NEXT:   50:       eddd4b02
+; IASM-NEXT:    vldr    d20, [sp, #8]
+
+; ASM-NEXT:     vadd.f64        d22, d22, d20
+; DIS-NEXT:   54:       ee766ba4
+; IASM-NEXT:    .byte 0xa4
+; IASM-NEXT:    .byte 0x6b
+; IASM-NEXT:    .byte 0x76
+; IASM-NEXT:    .byte 0xee
 
   ret double %res
 }