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| 1 //===- subzero/src/IceRegistersARM32.h - Register information ---*- C++ -*-===// | 1 //===- subzero/src/IceRegistersARM32.h - Register information ---*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 42 static constexpr std::size_t value = 1 + __length<U...>::value; | 42 static constexpr std::size_t value = 1 + __length<U...>::value; |
| 43 }; | 43 }; |
| 44 | 44 |
| 45 template <typename T> struct __length<T> { | 45 template <typename T> struct __length<T> { |
| 46 static constexpr std::size_t value = 1; | 46 static constexpr std::size_t value = 1; |
| 47 }; | 47 }; |
| 48 | 48 |
| 49 const std::size_t Size; | 49 const std::size_t Size; |
| 50 }; | 50 }; |
| 51 | 51 |
| 52 // TODO(kschimpf) Change this class to a namespace. | |
|
Jim Stichnoth
2016/01/14 22:04:19
I think you should just revert this file entirely,
Karl
2016/01/14 23:54:51
Reverted.
| |
| 52 class RegARM32 { | 53 class RegARM32 { |
| 53 private: | 54 private: |
| 54 RegARM32() = delete; | 55 RegARM32() = delete; |
| 55 RegARM32(const RegARM32 &) = delete; | 56 RegARM32(const RegARM32 &) = delete; |
| 56 RegARM32 &operator=(const RegARM32 &) = delete; | 57 RegARM32 &operator=(const RegARM32 &) = delete; |
| 57 ~RegARM32() = delete; | 58 ~RegARM32() = delete; |
| 58 | 59 |
| 59 public: | 60 public: |
| 60 /// An enum of every register. The enum value may not match the encoding used | 61 /// An enum of every register. The enum value may not match the encoding used |
| 61 /// to binary encode register operands in instructions. | 62 /// to binary encode register operands in instructions. |
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| 139 { \ | 140 { \ |
| 140 name, encode, cc_arg, scratch, preserved, stackptr, frameptr, isGPR, \ | 141 name, encode, cc_arg, scratch, preserved, stackptr, frameptr, isGPR, \ |
| 141 isInt, isI64Pair, isFP32, isFP64, isVec128, \ | 142 isInt, isI64Pair, isFP32, isFP64, isVec128, \ |
| 142 (SizeOf alias_init).size(), alias_init \ | 143 (SizeOf alias_init).size(), alias_init \ |
| 143 } \ | 144 } \ |
| 144 , | 145 , |
| 145 REGARM32_TABLE | 146 REGARM32_TABLE |
| 146 #undef X | 147 #undef X |
| 147 }; | 148 }; |
| 148 | 149 |
| 149 static inline void assertRegisterDefined(int32_t RegNum) { | 150 static void assertRegisterDefined(int32_t RegNum) { |
| 150 (void)RegNum; | 151 (void)RegNum; |
| 151 assert(RegNum >= 0); | 152 assert(RegNum >= 0); |
| 152 assert(RegNum < Reg_NUM); | 153 assert(RegNum < Reg_NUM); |
| 153 } | 154 } |
| 154 | 155 |
| 155 static inline bool isGPRegister(int32_t RegNum) { | 156 static bool isGPRegister(int32_t RegNum) { |
| 156 assertRegisterDefined(RegNum); | 157 assertRegisterDefined(RegNum); |
| 157 return Table[RegNum].IsGPR; | 158 return Table[RegNum].IsGPR; |
| 158 } | 159 } |
| 159 | 160 |
| 160 static constexpr SizeT getNumGPRegs() { | 161 static constexpr SizeT getNumGPRegs() { |
| 161 return 0 | 162 return 0 |
| 162 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ | 163 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ |
| 163 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ | 164 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
| 164 +(isGPR) | 165 +(isGPR) |
| 165 REGARM32_TABLE | 166 REGARM32_TABLE |
| 166 #undef X | 167 #undef X |
| 167 ; | 168 ; |
| 168 } | 169 } |
| 169 | 170 |
| 170 static inline GPRRegister getEncodedGPR(int32_t RegNum) { | 171 static GPRRegister getEncodedGPR(int32_t RegNum) { |
| 171 assert(isGPRegister(RegNum)); | 172 assert(isGPRegister(RegNum)); |
| 172 return GPRRegister(Table[RegNum].Encoding); | 173 return GPRRegister(Table[RegNum].Encoding); |
| 173 } | 174 } |
| 174 | 175 |
| 175 static constexpr SizeT getNumGPRs() { | 176 static constexpr SizeT getNumGPRs() { |
| 176 return 0 | 177 return 0 |
| 177 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ | 178 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ |
| 178 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ | 179 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
| 179 +(isGPR) | 180 +(isGPR) |
| 180 REGARM32_TABLE | 181 REGARM32_TABLE |
| 181 #undef X | 182 #undef X |
| 182 ; | 183 ; |
| 183 } | 184 } |
| 184 | 185 |
| 185 static inline bool isGPR(SizeT RegNum) { | 186 static bool isGPR(SizeT RegNum) { |
| 186 assertRegisterDefined(RegNum); | 187 assertRegisterDefined(RegNum); |
| 187 return Table[RegNum].IsGPR; | 188 return Table[RegNum].IsGPR; |
| 188 } | 189 } |
| 189 | 190 |
| 190 static inline IceString getGPRName(SizeT RegNum) { | 191 static IceString getGPRName(SizeT RegNum) { |
|
Jim Stichnoth
2016/01/14 22:04:19
This would more accurately be named getRegName(),
Karl
2016/01/14 23:54:51
Acknowledged.
| |
| 191 assert(isGPR(RegNum)); | 192 assert(isGPR(RegNum)); |
| 192 return Table[RegNum].Name; | 193 return Table[RegNum].Name; |
| 193 } | 194 } |
| 194 | 195 |
| 195 static inline GPRRegister getI64PairFirstGPRNum(int32_t RegNum) { | 196 static GPRRegister getI64PairFirstGPRNum(int32_t RegNum) { |
| 196 assert(isI64RegisterPair(RegNum)); | 197 assert(isI64RegisterPair(RegNum)); |
| 197 return GPRRegister(Table[RegNum].Encoding); | 198 return GPRRegister(Table[RegNum].Encoding); |
| 198 } | 199 } |
| 199 | 200 |
| 200 static inline GPRRegister getI64PairSecondGPRNum(int32_t RegNum) { | 201 static GPRRegister getI64PairSecondGPRNum(int32_t RegNum) { |
| 201 assert(isI64RegisterPair(RegNum)); | 202 assert(isI64RegisterPair(RegNum)); |
| 202 return GPRRegister(Table[RegNum].Encoding + 1); | 203 return GPRRegister(Table[RegNum].Encoding + 1); |
| 203 } | 204 } |
| 204 | 205 |
| 205 static inline bool isI64RegisterPair(int32_t RegNum) { | 206 static bool isI64RegisterPair(int32_t RegNum) { |
| 206 assertRegisterDefined(RegNum); | 207 assertRegisterDefined(RegNum); |
| 207 return Table[RegNum].IsI64Pair; | 208 return Table[RegNum].IsI64Pair; |
| 208 } | 209 } |
| 209 | 210 |
| 210 static inline bool isEncodedSReg(int32_t RegNum) { | 211 static bool isEncodedSReg(int32_t RegNum) { |
| 211 assertRegisterDefined(RegNum); | 212 assertRegisterDefined(RegNum); |
| 212 return Table[RegNum].IsFP32; | 213 return Table[RegNum].IsFP32; |
| 213 } | 214 } |
| 214 | 215 |
| 215 static constexpr SizeT getNumSRegs() { | 216 static constexpr SizeT getNumSRegs() { |
| 216 return 0 | 217 return 0 |
| 217 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ | 218 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ |
| 218 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ | 219 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
| 219 +(isFP32) | 220 +(isFP32) |
| 220 REGARM32_TABLE | 221 REGARM32_TABLE |
| 221 #undef X | 222 #undef X |
| 222 ; | 223 ; |
| 223 } | 224 } |
| 224 | 225 |
| 225 static inline IceString getSRegName(SizeT RegNum) { | 226 static IceString getSRegName(SizeT RegNum) { |
| 226 assert(isEncodedSReg(RegNum)); | 227 assert(isEncodedSReg(RegNum)); |
| 227 return Table[RegNum].Name; | 228 return Table[RegNum].Name; |
| 228 } | 229 } |
| 229 | 230 |
| 230 static inline SRegister getEncodedSReg(int32_t RegNum) { | 231 static SRegister getEncodedSReg(int32_t RegNum) { |
| 231 assert(isEncodedSReg(RegNum)); | 232 assert(isEncodedSReg(RegNum)); |
| 232 return SRegister(Table[RegNum].Encoding); | 233 return SRegister(Table[RegNum].Encoding); |
| 233 } | 234 } |
| 234 | 235 |
| 235 static inline bool isEncodedDReg(int32_t RegNum) { | 236 static bool isEncodedDReg(int32_t RegNum) { |
| 236 assertRegisterDefined(RegNum); | 237 assertRegisterDefined(RegNum); |
| 237 return Table[RegNum].IsFP64; | 238 return Table[RegNum].IsFP64; |
| 238 } | 239 } |
| 239 | 240 |
| 240 static constexpr inline SizeT getNumDRegs() { | 241 static constexpr SizeT getNumDRegs() { |
| 241 return 0 | 242 return 0 |
| 242 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ | 243 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ |
| 243 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ | 244 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
| 244 +(isFP64) | 245 +(isFP64) |
| 245 REGARM32_TABLE | 246 REGARM32_TABLE |
| 246 #undef X | 247 #undef X |
| 247 ; | 248 ; |
| 248 } | 249 } |
| 249 | 250 |
| 250 static inline DRegister getEncodedDReg(int32_t RegNum) { | 251 static DRegister getEncodedDReg(int32_t RegNum) { |
| 251 assert(isEncodedDReg(RegNum)); | 252 assert(isEncodedDReg(RegNum)); |
| 252 return DRegister(Table[RegNum].Encoding); | 253 return DRegister(Table[RegNum].Encoding); |
| 253 } | 254 } |
| 254 | 255 |
| 255 static inline bool isEncodedQReg(int32_t RegNum) { | 256 static bool isEncodedQReg(int32_t RegNum) { |
| 256 assertRegisterDefined(RegNum); | 257 assertRegisterDefined(RegNum); |
| 257 return Table[RegNum].IsVec128; | 258 return Table[RegNum].IsVec128; |
| 258 } | 259 } |
| 259 | 260 |
| 260 static inline QRegister getEncodedQReg(int32_t RegNum) { | 261 static QRegister getEncodedQReg(int32_t RegNum) { |
| 261 assert(isEncodedQReg(RegNum)); | 262 assert(isEncodedQReg(RegNum)); |
| 262 return QRegister(Table[RegNum].Encoding); | 263 return QRegister(Table[RegNum].Encoding); |
| 263 } | 264 } |
| 264 | 265 |
| 265 static inline IceString getRegName(int32_t RegNum) { | 266 static IceString getRegName(int32_t RegNum) { |
| 266 assertRegisterDefined(RegNum); | 267 assertRegisterDefined(RegNum); |
| 267 return Table[RegNum].Name; | 268 return Table[RegNum].Name; |
| 268 } | 269 } |
| 269 }; | 270 }; |
| 270 | 271 |
| 271 // Extend enum RegClass with ARM32-specific register classes (if any). | 272 // Extend enum RegClass with ARM32-specific register classes (if any). |
| 272 enum RegClassARM32 : uint8_t { RCARM32_NUM = RC_Target }; | 273 enum RegClassARM32 : uint8_t { RCARM32_NUM = RC_Target }; |
| 273 | 274 |
| 274 } // end of namespace ARM32 | 275 } // end of namespace ARM32 |
| 275 } // end of namespace Ice | 276 } // end of namespace Ice |
| 276 | 277 |
| 277 #endif // SUBZERO_SRC_ICEREGISTERSARM32_H | 278 #endif // SUBZERO_SRC_ICEREGISTERSARM32_H |
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