Add VMULS and VMULD instructions to integrated ARM assembler.

src/IceAssemblerARM32.cpp

Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 396f8f8b1cb0311a97e65ecef296c9a0e709471a..f90a890e033252e817772ba7708efaf58213f30b 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -2061,7 +2061,7 @@ void AssemblerARM32::vaddd(const Operand *OpDd, const Operand *OpDn,
   // VADD (floating-point) - ARM section A8.8.283, encoding A2:
   //   vadd<c>.f64 <Dd>, <Dn>, <Dm>
   //
-  // cccc11100D11nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
+  // cccc11100D10nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
   // and Mmmmm=Rm.
   constexpr const char *Vaddd = "vaddd";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vaddd);
@@ -2071,6 +2071,36 @@ void AssemblerARM32::vaddd(const Operand *OpDd, const Operand *OpDn,
   emitVFPddd(Cond, VadddOpcode, Dd, Dn, Dm);
 }
 
+void AssemblerARM32::vmuls(const Operand *OpSd, const Operand *OpSn,
+                           const Operand *OpSm, CondARM32::Cond Cond) {
+  // VMUL (floating-point) - ARM section A8.8.351, encoding A2:
+  //   vmul<c>.f32 <Sd>, <Sn>, <Sm>
+  //
+  // cccc11100D10nnnndddd101sN0M0mmmm where cccc=Cond, s=0, ddddD=Rd, nnnnN=Rn,
+  // and mmmmM=Rm.
+  constexpr const char *Vmuls = "vmuls";
+  IValueT Sd = encodeSRegister(OpSd, "Sd", Vmuls);
+  IValueT Sn = encodeSRegister(OpSn, "Sn", Vmuls);
+  IValueT Sm = encodeSRegister(OpSm, "Sm", Vmuls);
+  constexpr IValueT VmulsOpcode = B21;
+  emitVFPsss(Cond, VmulsOpcode, Sd, Sn, Sm);
+}
+
+void AssemblerARM32::vmuld(const Operand *OpDd, const Operand *OpDn,
+                           const Operand *OpDm, CondARM32::Cond Cond) {
+  // VMUL (floating-point) - ARM section A8.8.351, encoding A2:
+  //   vmul<c>.f64 <Dd>, <Dn>, <Dm>
+  //
+  // cccc11100D11nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
+  // and Mmmmm=Rm.
+  constexpr const char *Vmuld = "vmuld";
+  IValueT Dd = encodeDRegister(OpDd, "Dd", Vmuld);
+  IValueT Dn = encodeDRegister(OpDn, "Dn", Vmuld);
+  IValueT Dm = encodeDRegister(OpDm, "Dm", Vmuld);
+  constexpr IValueT VmuldOpcode = B21;
+  emitVFPddd(Cond, VmuldOpcode, Dd, Dn, Dm);
+}
+
 void AssemblerARM32::emitVStackOp(CondARM32::Cond Cond, IValueT Opcode,
                                   const Variable *OpBaseReg,
                                   SizeT NumConsecRegs) {