Add VDIVS and VDIVD instructions to the integrated ARM assembler.

src/IceAssemblerARM32.cpp

Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index a260a1e85d68a6fd7e544410517823a0fc635f65..18dadaab144b720766e4ac570152ec1a40eb34c4 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -2071,6 +2071,36 @@ void AssemblerARM32::vaddd(const Operand *OpDd, const Operand *OpDn,
   emitVFPddd(Cond, VadddOpcode, Dd, Dn, Dm);
 }
 
+void AssemblerARM32::vdivs(const Operand *OpSd, const Operand *OpSn,
+                           const Operand *OpSm, CondARM32::Cond Cond) {
+  // VDIV (floating-point) - ARM section A8.8.283, encoding A2:
+  //   vdiv<c>.f32 <Sd>, <Sn>, <Sm>
+  //
+  // cccc11101D00nnnndddd101sN0M0mmmm where cccc=Cond, s=0, ddddD=Rd, nnnnN=Rn,
+  // and mmmmM=Rm.
+  constexpr const char *Vdivs = "vdivs";
+  IValueT Sd = encodeSRegister(OpSd, "Sd", Vdivs);
+  IValueT Sn = encodeSRegister(OpSn, "Sn", Vdivs);
+  IValueT Sm = encodeSRegister(OpSm, "Sm", Vdivs);
+  constexpr IValueT VdivsOpcode = B23;
+  emitVFPsss(Cond, VdivsOpcode, Sd, Sn, Sm);
+}
+
+void AssemblerARM32::vdivd(const Operand *OpDd, const Operand *OpDn,
+                           const Operand *OpDm, CondARM32::Cond Cond) {
+  // VDIV (floating-point) - ARM section A8.8.283, encoding A2:
+  //   vdiv<c>.f64 <Dd>, <Dn>, <Dm>
+  //
+  // cccc11101D00nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
+  // and Mmmmm=Rm.
+  constexpr const char *Vdivd = "vdivd";
+  IValueT Dd = encodeDRegister(OpDd, "Dd", Vdivd);
+  IValueT Dn = encodeDRegister(OpDn, "Dn", Vdivd);
+  IValueT Dm = encodeDRegister(OpDm, "Dm", Vdivd);
+  constexpr IValueT VdivdOpcode = B23;
+  emitVFPddd(Cond, VdivdOpcode, Dd, Dn, Dm);
+}
+
 void AssemblerARM32::vsubs(const Operand *OpSd, const Operand *OpSn,
                            const Operand *OpSm, CondARM32::Cond Cond) {
   // VSUB (floating-point) - ARM section A8.8.415, encoding A2:
@@ -2078,27 +2108,27 @@ void AssemblerARM32::vsubs(const Operand *OpSd, const Operand *OpSn,
   //
   // cccc11100D11nnnndddd101sN1M0mmmm where cccc=Cond, s=0, ddddD=Rd, nnnnN=Rn,
   // and mmmmM=Rm.
-  constexpr const char *Vadds = "vsubs";
-  IValueT Sd = encodeSRegister(OpSd, "Sd", Vadds);
-  IValueT Sn = encodeSRegister(OpSn, "Sn", Vadds);
-  IValueT Sm = encodeSRegister(OpSm, "Sm", Vadds);
-  constexpr IValueT VaddsOpcode = B21 | B20 | B6;
-  emitVFPsss(Cond, VaddsOpcode, Sd, Sn, Sm);
+  constexpr const char *Vsubs = "vsubs";
+  IValueT Sd = encodeSRegister(OpSd, "Sd", Vsubs);
+  IValueT Sn = encodeSRegister(OpSn, "Sn", Vsubs);
+  IValueT Sm = encodeSRegister(OpSm, "Sm", Vsubs);
+  constexpr IValueT VsubsOpcode = B21 | B20 | B6;
+  emitVFPsss(Cond, VsubsOpcode, Sd, Sn, Sm);
 }
 
 void AssemblerARM32::vsubd(const Operand *OpDd, const Operand *OpDn,
                            const Operand *OpDm, CondARM32::Cond Cond) {
   // VSUB (floating-point) - ARM section A8.8.415, encoding A2:
-  //   vadd<c>.f64 <Dd>, <Dn>, <Dm>
+  //   vsub<c>.f64 <Dd>, <Dn>, <Dm>
   //
   // cccc11100D11nnnndddd101sN1M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
   // and Mmmmm=Rm.
-  constexpr const char *Vaddd = "vsubd";
-  IValueT Dd = encodeDRegister(OpDd, "Dd", Vaddd);
-  IValueT Dn = encodeDRegister(OpDn, "Dn", Vaddd);
-  IValueT Dm = encodeDRegister(OpDm, "Dm", Vaddd);
-  constexpr IValueT VadddOpcode = B21 | B20 | B6;
-  emitVFPddd(Cond, VadddOpcode, Dd, Dn, Dm);
+  constexpr const char *Vsubd = "vsubd";
+  IValueT Dd = encodeDRegister(OpDd, "Dd", Vsubd);
+  IValueT Dn = encodeDRegister(OpDn, "Dn", Vsubd);
+  IValueT Dm = encodeDRegister(OpDm, "Dm", Vsubd);
+  constexpr IValueT VsubdOpcode = B21 | B20 | B6;
+  emitVFPddd(Cond, VsubdOpcode, Dd, Dn, Dm);
 }
 
 void AssemblerARM32::emitVStackOp(CondARM32::Cond Cond, IValueT Opcode,