Add vcvt<c>.f32.f64 and vcvt<c>.f64.32 to ARM.

src/IceAssemblerARM32.h

Index: src/IceAssemblerARM32.h
diff --git a/src/IceAssemblerARM32.h b/src/IceAssemblerARM32.h
index 86a6807d76d2b9a88f3490670e6b90a5102f2f3f..f81fd6d5f5fe2ec37c7cbe3106941f22bc0a2fbf 100644
--- a/src/IceAssemblerARM32.h
+++ b/src/IceAssemblerARM32.h
@@ -324,6 +324,10 @@ public:
   void vadds(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm,
              CondARM32::Cond Cond);
 
+  void vcvtsd(const Operand *OpSd, const Operand *OpDm, CondARM32::Cond Cond);
+
+  void vcvtds(const Operand *OpDd, const Operand *OpSm, CondARM32::Cond Cond);
+
   void vdivd(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm,
              CondARM32::Cond Cond);
 
@@ -448,6 +452,14 @@ private:
   void emitVStackOp(CondARM32::Cond Cond, IValueT Opcode,
                     const Variable *OpBaseReg, SizeT NumConsecRegs);
 
+  // Pattern cccc111xxDxxxxxxdddd101xxxMxmmmm where cccc=Cond, ddddD=Sd,
+  // Mmmmm=Dm, and xx0xxxxxxdddd000xxx0x0000=Opcode.
+  void emitVFPsd(CondARM32::Cond Cond, IValueT Opcode, IValueT Sd, IValueT Dm);
+
+  // Pattern cccc111xxDxxxxxxdddd101xxxMxmmmm where cccc=Cond, Ddddd=Dd,
+  // mmmmM=Sm, and xx0xxxxxxdddd000xxx0x0000=Opcode.
+  void emitVFPds(CondARM32::Cond Cond, IValueT Opcode, IValueT Dd, IValueT Sm);
+
   // Pattern cccc011100x1dddd1111mmmm0001nnn where cccc=Cond,
   // x=Opcode, dddd=Rd, nnnn=Rn, mmmm=Rm.
   void emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,