Add vcvt<c>.f32.f64 and vcvt<c>.f64.32 to ARM.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1864 matching lines @@
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   assert(getDest()->hasReg());
   Str << "\t"
          "vcvt" << getPredicate() << vcvtVariantSuffix(Variant) << "\t";
   getDest()->emit(Func);
   Str << ", ";
   getSrc(0)->emit(Func);
 }
 
+void InstARM32Vcvt::emitIAS(const Cfg *Func) const {
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  switch (Variant) {
+  case S2d:
+    Asm->vcvtds(getDest(), getSrc(0), getPredicate());
+    break;
+  case D2s:
+    Asm->vcvtsd(getDest(), getSrc(0), getPredicate());
+    break;
+  default:
+    // TODO(kschimpf): Fill in other variants.
+    Asm->setNeedsTextFixup();
+    break;
+  }
+  if (Asm->needsTextFixup())
+    emitUsingTextFixup(Func);
+}
+
 void InstARM32Vcvt::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   dumpDest(Func);
   Str << " = "
       << "vcvt" << getPredicate() << vcvtVariantSuffix(Variant) << " ";
   dumpSources(Func);
 }
 
@@ skipping 329 matching lines @@
 
 template class InstARM32FourAddrGPR<InstARM32::Mla>;
 template class InstARM32FourAddrGPR<InstARM32::Mls>;
 
 template class InstARM32CmpLike<InstARM32::Cmn>;
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
 } // end of namespace ARM32
 } // end of namespace Ice