Add vcvt<c>.f32.f64 and vcvt<c>.f64.32 to ARM.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 2053 matching lines @@
   // cccc11100D11nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
   // and Mmmmm=Rm.
   constexpr const char *Vaddd = "vaddd";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vaddd);
   IValueT Dn = encodeDRegister(OpDn, "Dn", Vaddd);
   IValueT Dm = encodeDRegister(OpDm, "Dm", Vaddd);
   constexpr IValueT VadddOpcode = B21 | B20;
   emitVFPddd(Cond, VadddOpcode, Dd, Dn, Dm);
 }
 
+void AssemblerARM32::emitVFPsd(CondARM32::Cond Cond, IValueT Opcode, IValueT Sd,
+                               IValueT Dm) {
+  assert(Sd < RegARM32::getNumSRegs());
+  assert(Dm < RegARM32::getNumDRegs());
+  assert(CondARM32::isDefined(Cond));
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9;
+  const IValueT Encoding =
+      Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) |
+      (getYInRegXXXXY(Sd) << 22) | (getXXXXInRegXXXXY(Sd) << 12) |
+      (getYInRegYXXXX(Dm) << 5) | getXXXXInRegYXXXX(Dm);
+  emitInst(Encoding);
+}
+
+void AssemblerARM32::vcvtsd(const Operand *OpSd, const Operand *OpDm,
+                            CondARM32::Cond Cond) {
+  constexpr const char *Vcvtsd = "vctsd";
+  IValueT Sd = encodeSRegister(OpSd, "Sd", Vcvtsd);
+  IValueT Dm = encodeDRegister(OpDm, "Dm", Vcvtsd);
+  constexpr IValueT VcvtsdOpcode =
+      B23 | B21 | B20 | B18 | B17 | B16 | B8 | B7 | B6;
+  emitVFPsd(Cond, VcvtsdOpcode, Sd, Dm);
+}
+
+void AssemblerARM32::emitVFPds(CondARM32::Cond Cond, IValueT Opcode, IValueT Dd,
+                               IValueT Sm) {
+  assert(Dd < RegARM32::getNumDRegs());
+  assert(Sm < RegARM32::getNumSRegs());
+  assert(CondARM32::isDefined(Cond));
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9;
+  const IValueT Encoding =
+      Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) |
+      (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dd) << 12) |
+      (getYInRegXXXXY(Sm) << 5) | getXXXXInRegXXXXY(Sm);
+  emitInst(Encoding);
+}
+
+void AssemblerARM32::vcvtds(const Operand *OpDd, const Operand *OpSm,
+                            CondARM32::Cond Cond) {
+  constexpr const char *Vcvtds = "Vctds";
+  IValueT Dd = encodeDRegister(OpDd, "Dd", Vcvtds);
+  IValueT Sm = encodeSRegister(OpSm, "Sm", Vcvtds);
+  constexpr IValueT VcvtdsOpcode = B23 | B21 | B20 | B18 | B17 | B16 | B7 | B6;
+  emitVFPds(Cond, VcvtdsOpcode, Dd, Sm);
+}
+
 void AssemblerARM32::vdivs(const Operand *OpSd, const Operand *OpSn,
                            const Operand *OpSm, CondARM32::Cond Cond) {
   // VDIV (floating-point) - ARM section A8.8.283, encoding A2:
   //   vdiv<c>.f32 <Sd>, <Sn>, <Sm>
   //
   // cccc11101D00nnnndddd101sN0M0mmmm where cccc=Cond, s=0, ddddD=Rd, nnnnN=Rn,
   // and mmmmM=Rm.
   constexpr const char *Vdivs = "vdivs";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vdivs);
   IValueT Sn = encodeSRegister(OpSn, "Sn", Vdivs);
@@ skipping 119 matching lines @@
   //
   // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr IValueT VpushOpcode =
       B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
   emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice