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Side by Side Diff: src/DartARM32/assembler_arm.cc

Issue 1567623008: Add vcvt<c>.f32.f64 and vcvt<c>.f64.32 to ARM. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 4 years, 11 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 // 4 //
5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe
6 // Please update the (git) revision if we merge changes from Dart. 6 // Please update the (git) revision if we merge changes from Dart.
7 // https://code.google.com/p/dart/wiki/GettingTheSource 7 // https://code.google.com/p/dart/wiki/GettingTheSource
8 8
9 #include "vm/globals.h" // NOLINT 9 #include "vm/globals.h" // NOLINT
10 #if defined(TARGET_ARCH_ARM) 10 #if defined(TARGET_ARCH_ARM)
(...skipping 1049 matching lines...) Expand 10 before | Expand all | Expand 10 after
1060 1060
1061 1061
1062 void Assembler::vsqrts(SRegister sd, SRegister sm, Condition cond) { 1062 void Assembler::vsqrts(SRegister sd, SRegister sm, Condition cond) {
1063 EmitVFPsss(cond, B23 | B21 | B20 | B16 | B7 | B6, sd, S0, sm); 1063 EmitVFPsss(cond, B23 | B21 | B20 | B16 | B7 | B6, sd, S0, sm);
1064 } 1064 }
1065 1065
1066 void Assembler::vsqrtd(DRegister dd, DRegister dm, Condition cond) { 1066 void Assembler::vsqrtd(DRegister dd, DRegister dm, Condition cond) {
1067 EmitVFPddd(cond, B23 | B21 | B20 | B16 | B7 | B6, dd, D0, dm); 1067 EmitVFPddd(cond, B23 | B21 | B20 | B16 | B7 | B6, dd, D0, dm);
1068 } 1068 }
1069 1069
1070 1070 #if 0
1071 // Moved to ARM32::AssemblerARM32::emitVFPsd
1071 void Assembler::EmitVFPsd(Condition cond, int32_t opcode, 1072 void Assembler::EmitVFPsd(Condition cond, int32_t opcode,
1072 SRegister sd, DRegister dm) { 1073 SRegister sd, DRegister dm) {
1073 ASSERT(TargetCPUFeatures::vfp_supported()); 1074 ASSERT(TargetCPUFeatures::vfp_supported());
1074 ASSERT(sd != kNoSRegister); 1075 ASSERT(sd != kNoSRegister);
1075 ASSERT(dm != kNoDRegister); 1076 ASSERT(dm != kNoDRegister);
1076 ASSERT(cond != kNoCondition); 1077 ASSERT(cond != kNoCondition);
1077 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 1078 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
1078 B27 | B26 | B25 | B11 | B9 | opcode | 1079 B27 | B26 | B25 | B11 | B9 | opcode |
1079 ((static_cast<int32_t>(sd) & 1)*B22) | 1080 ((static_cast<int32_t>(sd) & 1)*B22) |
1080 ((static_cast<int32_t>(sd) >> 1)*B12) | 1081 ((static_cast<int32_t>(sd) >> 1)*B12) |
1081 ((static_cast<int32_t>(dm) >> 4)*B5) | 1082 ((static_cast<int32_t>(dm) >> 4)*B5) |
1082 (static_cast<int32_t>(dm) & 0xf); 1083 (static_cast<int32_t>(dm) & 0xf);
1083 Emit(encoding); 1084 Emit(encoding);
1084 } 1085 }
1085 1086
1086 1087 // Moved to ARM32::AssemblerARM32::emitVFPds
1087 void Assembler::EmitVFPds(Condition cond, int32_t opcode, 1088 void Assembler::EmitVFPds(Condition cond, int32_t opcode,
1088 DRegister dd, SRegister sm) { 1089 DRegister dd, SRegister sm) {
1089 ASSERT(TargetCPUFeatures::vfp_supported()); 1090 ASSERT(TargetCPUFeatures::vfp_supported());
1090 ASSERT(dd != kNoDRegister); 1091 ASSERT(dd != kNoDRegister);
1091 ASSERT(sm != kNoSRegister); 1092 ASSERT(sm != kNoSRegister);
1092 ASSERT(cond != kNoCondition); 1093 ASSERT(cond != kNoCondition);
1093 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 1094 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
1094 B27 | B26 | B25 | B11 | B9 | opcode | 1095 B27 | B26 | B25 | B11 | B9 | opcode |
1095 ((static_cast<int32_t>(dd) >> 4)*B22) | 1096 ((static_cast<int32_t>(dd) >> 4)*B22) |
1096 ((static_cast<int32_t>(dd) & 0xf)*B12) | 1097 ((static_cast<int32_t>(dd) & 0xf)*B12) |
1097 ((static_cast<int32_t>(sm) & 1)*B5) | 1098 ((static_cast<int32_t>(sm) & 1)*B5) |
1098 (static_cast<int32_t>(sm) >> 1); 1099 (static_cast<int32_t>(sm) >> 1);
1099 Emit(encoding); 1100 Emit(encoding);
1100 } 1101 }
1101 1102
1102 1103 // Moved to ARM32::AssemblerARM32::vcvtsd().
1103 void Assembler::vcvtsd(SRegister sd, DRegister dm, Condition cond) { 1104 void Assembler::vcvtsd(SRegister sd, DRegister dm, Condition cond) {
1104 EmitVFPsd(cond, B23 | B21 | B20 | B18 | B17 | B16 | B8 | B7 | B6, sd, dm); 1105 EmitVFPsd(cond, B23 | B21 | B20 | B18 | B17 | B16 | B8 | B7 | B6, sd, dm);
1105 } 1106 }
1106 1107
1107 1108 // Moved to ARM32::AssemblerARM32::vcvtds().
1108 void Assembler::vcvtds(DRegister dd, SRegister sm, Condition cond) { 1109 void Assembler::vcvtds(DRegister dd, SRegister sm, Condition cond) {
1109 EmitVFPds(cond, B23 | B21 | B20 | B18 | B17 | B16 | B7 | B6, dd, sm); 1110 EmitVFPds(cond, B23 | B21 | B20 | B18 | B17 | B16 | B7 | B6, dd, sm);
1110 } 1111 }
1112 #endif
1111 1113
1112 1114
1113 void Assembler::vcvtis(SRegister sd, SRegister sm, Condition cond) { 1115 void Assembler::vcvtis(SRegister sd, SRegister sm, Condition cond) {
1114 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm); 1116 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm);
1115 } 1117 }
1116 1118
1117 1119
1118 void Assembler::vcvtid(SRegister sd, DRegister dm, Condition cond) { 1120 void Assembler::vcvtid(SRegister sd, DRegister dm, Condition cond) {
1119 EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B16 | B8 | B7 | B6, sd, dm); 1121 EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B16 | B8 | B7 | B6, sd, dm);
1120 } 1122 }
(...skipping 2564 matching lines...) Expand 10 before | Expand all | Expand 10 after
3685 3687
3686 3688
3687 const char* Assembler::FpuRegisterName(FpuRegister reg) { 3689 const char* Assembler::FpuRegisterName(FpuRegister reg) {
3688 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); 3690 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
3689 return fpu_reg_names[reg]; 3691 return fpu_reg_names[reg];
3690 } 3692 }
3691 3693
3692 } // namespace dart 3694 } // namespace dart
3693 3695
3694 #endif // defined TARGET_ARCH_ARM 3696 #endif // defined TARGET_ARCH_ARM
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