Add VCMP{s,sz,d,dz} Instructions to ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 992 matching lines @@
                                 IValueT Dd, IValueT Dn, IValueT Dm) {
   assert(Dd < RegARM32::getNumDRegs());
   assert(Dn < RegARM32::getNumDRegs());
   assert(Dm < RegARM32::getNumDRegs());
   assert(CondARM32::isDefined(Cond));
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9 | B8;
   const IValueT Encoding =
       Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) |
       (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) |
-      (getXXXXInRegYXXXX(Dn) << 12) | (getYInRegYXXXX(Dn) << 7) |
+      (getXXXXInRegYXXXX(Dd) << 12) | (getYInRegYXXXX(Dn) << 7) |
       (getYInRegYXXXX(Dm) << 5) | getXXXXInRegYXXXX(Dm);
   emitInst(Encoding);
 }
 
 void AssemblerARM32::emitVFPsss(CondARM32::Cond Cond, IValueT Opcode,
                                 IValueT Sd, IValueT Sn, IValueT Sm) {
   assert(Sd < RegARM32::getNumSRegs());
   assert(Sn < RegARM32::getNumSRegs());
   assert(Sm < RegARM32::getNumSRegs());
   assert(CondARM32::isDefined(Cond));
@@ skipping 1040 matching lines @@
   // cccc11100D11nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
   // and Mmmmm=Rm.
   constexpr const char *Vaddd = "vaddd";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vaddd);
   IValueT Dn = encodeDRegister(OpDn, "Dn", Vaddd);
   IValueT Dm = encodeDRegister(OpDm, "Dm", Vaddd);
   constexpr IValueT VadddOpcode = B21 | B20;
   emitVFPddd(Cond, VadddOpcode, Dd, Dn, Dm);
 }
 
+void AssemblerARM32::vcmpd(const Operand *OpDd, const Operand *OpDm,
+                           CondARM32::Cond Cond) {
+  constexpr const char *Vcmpd = "vcmpd";
+  IValueT Dd = encodeDRegister(OpDd, "Dd", Vcmpd);
+  IValueT Dm = encodeDRegister(OpDm, "Dm", Vcmpd);
+  constexpr IValueT VcmpdOpcode = B23 | B21 | B20 | B18 | B6;
+  constexpr IValueT Dn = 0;
+  emitVFPddd(Cond, VcmpdOpcode, Dd, Dn, Dm);
+}
+
+void AssemblerARM32::vcmpdz(const Operand *OpDd, CondARM32::Cond Cond) {
+  constexpr const char *Vcmpdz = "vcmpdz";
+  IValueT Dd = encodeDRegister(OpDd, "Dd", Vcmpdz);
+  constexpr IValueT VcmpdzOpcode = B23 | B21 | B20 | B18 | B16 | B6;
+  constexpr IValueT Dn = 0;
+  constexpr IValueT Dm = 0;
+  emitVFPddd(Cond, VcmpdzOpcode, Dd, Dn, Dm);
+}
+
+void AssemblerARM32::vcmps(const Operand *OpSd, const Operand *OpSm,
+                           CondARM32::Cond Cond) {
+  constexpr const char *Vcmps = "vcmps";
+  IValueT Sd = encodeSRegister(OpSd, "Sd", Vcmps);
+  IValueT Sm = encodeSRegister(OpSm, "Sm", Vcmps);
+  constexpr IValueT VcmpsOpcode = B23 | B21 | B20 | B18 | B6;
+  constexpr IValueT Sn = 0;
+  emitVFPsss(Cond, VcmpsOpcode, Sd, Sn, Sm);
+}
+
+void AssemblerARM32::vcmpsz(const Operand *OpSd, CondARM32::Cond Cond) {
+  constexpr const char *Vcmpsz = "vcmps";
+  IValueT Sd = encodeSRegister(OpSd, "Sd", Vcmpsz);
+  constexpr IValueT VcmpszOpcode = B23 | B21 | B20 | B18 | B16 | B6;
+  constexpr IValueT Sn = 0;
+  constexpr IValueT Sm = 0;
+  emitVFPsss(Cond, VcmpszOpcode, Sd, Sn, Sm);
+}
+
 void AssemblerARM32::emitVFPsd(CondARM32::Cond Cond, IValueT Opcode, IValueT Sd,
                                IValueT Dm) {
   assert(Sd < RegARM32::getNumSRegs());
   assert(Dm < RegARM32::getNumDRegs());
   assert(CondARM32::isDefined(Cond));
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9;
   const IValueT Encoding =
       Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) |
       (getYInRegXXXXY(Sd) << 22) | (getXXXXInRegXXXXY(Sd) << 12) |
@@ skipping 166 matching lines @@
   //
   // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr IValueT VpushOpcode =
       B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
   emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice