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Issue 1564393002: Add VCMP{s,sz,d,dz} Instructions to ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nits. Created 4 years, 11 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 // 4 //
5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe
6 // Please update the (git) revision if we merge changes from Dart. 6 // Please update the (git) revision if we merge changes from Dart.
7 // https://code.google.com/p/dart/wiki/GettingTheSource 7 // https://code.google.com/p/dart/wiki/GettingTheSource
8 8
9 #include "vm/globals.h" // NOLINT 9 #include "vm/globals.h" // NOLINT
10 #if defined(TARGET_ARCH_ARM) 10 #if defined(TARGET_ARCH_ARM)
(...skipping 1135 matching lines...) Expand 10 before | Expand all | Expand 10 after
1146 1146
1147 void Assembler::vcvtsu(SRegister sd, SRegister sm, Condition cond) { 1147 void Assembler::vcvtsu(SRegister sd, SRegister sm, Condition cond) {
1148 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B6, sd, S0, sm); 1148 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B6, sd, S0, sm);
1149 } 1149 }
1150 1150
1151 1151
1152 void Assembler::vcvtdu(DRegister dd, SRegister sm, Condition cond) { 1152 void Assembler::vcvtdu(DRegister dd, SRegister sm, Condition cond) {
1153 EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B6, dd, sm); 1153 EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B6, dd, sm);
1154 } 1154 }
1155 1155
1156 1156 #if 0
1157 // Moved to ARM23::AssemblerARM32::vcmps().
1157 void Assembler::vcmps(SRegister sd, SRegister sm, Condition cond) { 1158 void Assembler::vcmps(SRegister sd, SRegister sm, Condition cond) {
1158 EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm); 1159 EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm);
1159 } 1160 }
1160 1161
1161 1162 // Moved to ARM23::AssemblerARM32::vcmpd().
1162 void Assembler::vcmpd(DRegister dd, DRegister dm, Condition cond) { 1163 void Assembler::vcmpd(DRegister dd, DRegister dm, Condition cond) {
1163 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm); 1164 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm);
1164 } 1165 }
1165 1166
1166 1167 // Moved to ARM23::AssemblerARM32::vcmpsz().
1167 void Assembler::vcmpsz(SRegister sd, Condition cond) { 1168 void Assembler::vcmpsz(SRegister sd, Condition cond) {
1168 EmitVFPsss(cond, B23 | B21 | B20 | B18 | B16 | B6, sd, S0, S0); 1169 EmitVFPsss(cond, B23 | B21 | B20 | B18 | B16 | B6, sd, S0, S0);
1169 } 1170 }
1170 1171
1171 1172 // Moved to ARM23::AssemblerARM32::vcmpdz().
1172 void Assembler::vcmpdz(DRegister dd, Condition cond) { 1173 void Assembler::vcmpdz(DRegister dd, Condition cond) {
1173 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0); 1174 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0);
1174 } 1175 }
1175 1176 #endif
1176 1177
1177 void Assembler::vmrs(Register rd, Condition cond) { 1178 void Assembler::vmrs(Register rd, Condition cond) {
1178 ASSERT(TargetCPUFeatures::vfp_supported()); 1179 ASSERT(TargetCPUFeatures::vfp_supported());
1179 ASSERT(cond != kNoCondition); 1180 ASSERT(cond != kNoCondition);
1180 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | 1181 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
1181 B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 | 1182 B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 |
1182 (static_cast<int32_t>(rd)*B12) | 1183 (static_cast<int32_t>(rd)*B12) |
1183 B11 | B9 | B4; 1184 B11 | B9 | B4;
1184 Emit(encoding); 1185 Emit(encoding);
1185 } 1186 }
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3689 3690
3690 3691
3691 const char* Assembler::FpuRegisterName(FpuRegister reg) { 3692 const char* Assembler::FpuRegisterName(FpuRegister reg) {
3692 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); 3693 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
3693 return fpu_reg_names[reg]; 3694 return fpu_reg_names[reg];
3694 } 3695 }
3695 3696
3696 } // namespace dart 3697 } // namespace dart
3697 3698
3698 #endif // defined TARGET_ARCH_ARM 3699 #endif // defined TARGET_ARCH_ARM
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