Add VCMP{s,sz,d,dz} Instructions to ARM integrated assembler.

tests_lit/assembler/arm32/vcmp.ll

+; Show that we know how to translate vcmp.
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \

[Jim Stichnoth, 2016/01/09 01:34:28]

Can you use -O2 like in many/most other tests, to simplify the output to test?

[Karl, 2016/01/11 16:42:20]

If you use -O2, you will get different register assignments. Since the register
mask CL is not ready yet, I limited it to -Om1.

On the other hand, I realized over the weekend that would could greatly simplify
these tests by taking advantage of the disassembly more. That is, we know the
vcmp instructions got translated if the dissassembly is the same, and if "vcmp"
does not appear in the hybrid assembly text.

Hence, I have simplified this test accordingly.

+; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -Om1 | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
+; RUN:   | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -Om1 | FileCheck %s --check-prefix=DIS
+
+define internal i32 @vcmpFloat(float %v1, float %v2) {
+; ASM-LABEL: vcmpFloat:
+; DIS-LABEL: 00000000 <vcmpFloat>:
+; IASM-LABEL: vcmpFloat:
+
+entry:
+; ASM-NEXT: .LvcmpFloat$entry:
+; IASM-NEXT: .LvcmpFloat$entry:
+
+; ASM-NEXT:     sub     sp, sp, #16
+; DIS-NEXT:    0:      e24dd010
+; IASM-NEXT:    .byte 0x10
+; IASM-NEXT:    .byte 0xd0
+; IASM-NEXT:    .byte 0x4d
+; IASM-NEXT:    .byte 0xe2
+
+; ASM-NEXT:     vstr    s0, [sp, #12]
+; ASM-NEXT:     # [sp, #12] = def.pseudo 
+; DIS-NEXT:    4:      ed8d0a03
+; IASM-NEXT:    vstr    s0, [sp, #12]
+
+; ASM-NEXT:     vstr    s1, [sp, #8]
+; ASM-NEXT:     # [sp, #8] = def.pseudo 
+; DIS-NEXT:    8:      edcd0a02
+; IASM-NEXT:    vstr    s1, [sp, #8]
+
+  %cmp = fcmp olt float %v1, %v2
+
+; ASM-NEXT:     vldr    s0, [sp, #12]
+; DIS-NEXT:    c:      ed9d0a03
+; IASM-NEXT:    vldr    s0, [sp, #12]
+
+; ASM-NEXT:     vldr    s1, [sp, #8]
+; DIS-NEXT:   10:      eddd0a02
+; IASM-NEXT:    vldr    s1, [sp, #8]
+
+; ASM-NEXT:     vcmp.f32        s0, s1
+; DIS-NEXT:   14:      eeb40a60
+; IASM-NEXT:    .byte 0x60
+; IASM-NEXT:    .byte 0xa
+; IASM-NEXT:    .byte 0xb4
+; IASM-NEXT:    .byte 0xee
+
+  %res = zext i1 %cmp to i32
+  ret i32 %res
+}
+
+define internal i32 @vcmpFloatToZero(float %v) {
+; ASM-LABEL: vcmpFloatToZero:
+; DIS-LABEL: 00000040 <vcmpFloatToZero>:
+; IASM-LABEL: vcmpFloatToZero:
+
+entry:
+; ASM-NEXT: .LvcmpFloatToZero$entry:
+; IASM-NEXT: .LvcmpFloatToZero$entry:
+
+; ASM-NEXT:     sub     sp, sp, #12
+; DIS-NEXT:   40:      e24dd00c
+; IASM-NEXT:    .byte 0xc
+; IASM-NEXT:    .byte 0xd0
+; IASM-NEXT:    .byte 0x4d
+; IASM-NEXT:    .byte 0xe2
+
+; ASM-NEXT:     vstr    s0, [sp, #8]
+; ASM-NEXT:     # [sp, #8] = def.pseudo 
+; DIS-NEXT:   44:      ed8d0a02
+; IASM-NEXT:    vstr    s0, [sp, #8]
+
+  %cmp = fcmp olt float %v, 0.0
+
+; ASM-NEXT:     vldr    s0, [sp, #8]
+; DIS-NEXT:   48:      ed9d0a02
+; IASM-NEXT:    vldr    s0, [sp, #8]
+
+; ASM-NEXT:     vcmp.f32        s0, #0.0
+; DIS-NEXT:   4c:      eeb50a40
+; IASM-NEXT:    .byte 0x40
+; IASM-NEXT:    .byte 0xa
+; IASM-NEXT:    .byte 0xb5
+; IASM-NEXT:    .byte 0xee
+
+  %res = zext i1 %cmp to i32
+  ret i32 %res
+}
+
+define internal i32 @vcmpDouble(double %v1, double %v2) {
+; ASM-LABEL: vcmpDouble:
+; DIS-LABEL: 00000080 <vcmpDouble>:
+; IASM-LABEL: vcmpDouble:
+
+entry:
+; ASM-NEXT: .LvcmpDouble$entry:
+; IASM-NEXT: .LvcmpDouble$entry:
+
+; ASM-NEXT:     sub     sp, sp, #24
+; DIS-NEXT:   80:      e24dd018
+; IASM-NEXT:    .byte 0x18
+; IASM-NEXT:    .byte 0xd0
+; IASM-NEXT:    .byte 0x4d
+; IASM-NEXT:    .byte 0xe2
+
+; ASM-NEXT:     vstr    d0, [sp, #16]
+; ASM-NEXT:     # [sp, #16] = def.pseudo 
+; DIS-NEXT:   84:      ed8d0b04
+; IASM-NEXT:    vstr    d0, [sp, #16]
+
+; ASM-NEXT:     vstr    d1, [sp, #8]
+; ASM-NEXT:     # [sp, #8] = def.pseudo 
+; DIS-NEXT:   88:      ed8d1b02
+; IASM-NEXT:    vstr    d1, [sp, #8]
+
+  %cmp = fcmp olt double %v1, %v2
+
+; ASM-NEXT:     vldr    d31, [sp, #16]
+; DIS-NEXT:   8c:      edddfb04
+; IASM-NEXT:    vldr    d31, [sp, #16]
+
+; ASM-NEXT:     vldr    d30, [sp, #8]
+; DIS-NEXT:   90:      edddeb02
+; IASM-NEXT:    vldr    d30, [sp, #8]
+
+; ASM-NEXT:     vcmp.f64        d31, d30
+; DIS-NEXT:   94:      eef4fb6e
+; IASM-NEXT:    .byte 0x6e
+; IASM-NEXT:    .byte 0xfb
+; IASM-NEXT:    .byte 0xf4
+; IASM-NEXT:    .byte 0xee
+
+  %res = zext i1 %cmp to i32
+  ret i32 %res
+}
+
+define internal i32 @vcmpDoubleToZero(double %v) {
+; ASM-LABEL: vcmpDoubleToZero:
+; DIS-LABEL: 000000c0 <vcmpDoubleToZero>:
+
+entry:
+; ASM-NEXT: .LvcmpDoubleToZero$entry:
+
+; ASM-NEXT:     sub     sp, sp, #16
+; DIS-NEXT:   c0:      e24dd010
+
+; ASM-NEXT:     vstr    d0, [sp, #8]
+; ASM-NEXT:     # [sp, #8] = def.pseudo 
+; DIS-NEXT:   c4:      ed8d0b02
+
+  %cmp = fcmp olt double %v, 0.0
+
+; ASM-NEXT:     vldr    d31, [sp, #8]
+; DIS-NEXT:   c8:      edddfb02
+
+; ASM-NEXT:     vcmp.f64        d31, #0.0
+; DIS-NEXT:   cc:      eef5fb40
+
+  %res = zext i1 %cmp to i32
+  ret i32 %res
+}