Add support for threading and atomic ops in QNX Neutrino.

base/atomicops_internals_arm_gcc.h

 // Copyright 2013 The Chromium Authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // This file is an internal atomic implementation, use base/atomicops.h instead.
 //
 // LinuxKernelCmpxchg and Barrier_AtomicIncrement are from Google Gears.
 
 #ifndef BASE_ATOMICOPS_INTERNALS_ARM_GCC_H_
 #define BASE_ATOMICOPS_INTERNALS_ARM_GCC_H_
 
+#if defined(OS_QNX)
+#include <sys/cpuinline.h>
+#endif
+
 namespace base {
 namespace subtle {
 
 // Memory barriers on ARM are funky, but the kernel is here to help:
 //
 // * ARMv5 didn't support SMP, there is no memory barrier instruction at
 //   all on this architecture, or when targeting its machine code.
 //
 // * Some ARMv6 CPUs support SMP. A full memory barrier can be produced by
 //   writing a random value to a very specific coprocessor register.
@@ skipping 11 matching lines @@
 //   core devices, this is an empty function that exits immediately.
 //   On multi-core devices, it implements a full memory barrier.
 //
 // * This source could be compiled to ARMv5 machine code that runs on a
 //   multi-core ARMv6 or ARMv7 device. In this case, memory barriers
 //   are needed for correct execution. Always call the kernel helper, even
 //   when targeting ARMv5TE.
 //
 
 inline void MemoryBarrier() {
-  // Note: This is a function call, which is also an implicit compiler
-  // barrier.
+#if defined(OS_LINUX) || defined(OS_ANDROID)
+  // Note: This is a function call, which is also an implicit compiler barrier.
   typedef void (*KernelMemoryBarrierFunc)();
   ((KernelMemoryBarrierFunc)0xffff0fa0)();
+#elif defined(OS_QNX)
+  __cpu_membarrier();
+#else
+#error MemoryBarrier() is not implemented on this platform.
+#endif
 }
 
 // An ARM toolchain would only define one of these depending on which
 // variant of the target architecture is being used. This tests against
 // any known ARMv6 or ARMv7 variant, where it is possible to directly
 // use ldrex/strex instructions to implement fast atomic operations.
 #if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || \
     defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) || \
     defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
     defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) || \
@@ skipping 219 matching lines @@
 
 inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
   MemoryBarrier();
   return *ptr;
 }
 
 }  // namespace base::subtle
 }  // namespace base
 
 #endif  // BASE_ATOMICOPS_INTERNALS_ARM_GCC_H_