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1 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=// | 1 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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438 | 438 |
439 template <typename T> struct __length<T> { | 439 template <typename T> struct __length<T> { |
440 static constexpr std::size_t value = 1; | 440 static constexpr std::size_t value = 1; |
441 }; | 441 }; |
442 | 442 |
443 const std::size_t Size; | 443 const std::size_t Size; |
444 }; | 444 }; |
445 | 445 |
446 public: | 446 public: |
447 static void initRegisterSet( | 447 static void initRegisterSet( |
| 448 const ::Ice::ClFlags & /*Flags*/, |
448 std::array<llvm::SmallBitVector, RCX86_NUM> *TypeToRegisterSet, | 449 std::array<llvm::SmallBitVector, RCX86_NUM> *TypeToRegisterSet, |
449 std::array<llvm::SmallBitVector, RegisterSet::Reg_NUM> *RegisterAliases, | 450 std::array<llvm::SmallBitVector, RegisterSet::Reg_NUM> *RegisterAliases, |
450 llvm::SmallBitVector *ScratchRegs) { | 451 llvm::SmallBitVector *ScratchRegs) { |
451 llvm::SmallBitVector IntegerRegistersI32(RegisterSet::Reg_NUM); | 452 llvm::SmallBitVector IntegerRegistersI32(RegisterSet::Reg_NUM); |
452 llvm::SmallBitVector IntegerRegistersI16(RegisterSet::Reg_NUM); | 453 llvm::SmallBitVector IntegerRegistersI16(RegisterSet::Reg_NUM); |
453 llvm::SmallBitVector IntegerRegistersI8(RegisterSet::Reg_NUM); | 454 llvm::SmallBitVector IntegerRegistersI8(RegisterSet::Reg_NUM); |
454 llvm::SmallBitVector FloatRegisters(RegisterSet::Reg_NUM); | 455 llvm::SmallBitVector FloatRegisters(RegisterSet::Reg_NUM); |
455 llvm::SmallBitVector VectorRegisters(RegisterSet::Reg_NUM); | 456 llvm::SmallBitVector VectorRegisters(RegisterSet::Reg_NUM); |
456 llvm::SmallBitVector Trunc64To8Registers(RegisterSet::Reg_NUM); | 457 llvm::SmallBitVector Trunc64To8Registers(RegisterSet::Reg_NUM); |
457 llvm::SmallBitVector Trunc32To8Registers(RegisterSet::Reg_NUM); | 458 llvm::SmallBitVector Trunc32To8Registers(RegisterSet::Reg_NUM); |
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529 (*TypeToRegisterSet)[RC_v4i32] = VectorRegisters; | 530 (*TypeToRegisterSet)[RC_v4i32] = VectorRegisters; |
530 (*TypeToRegisterSet)[RC_v4f32] = VectorRegisters; | 531 (*TypeToRegisterSet)[RC_v4f32] = VectorRegisters; |
531 (*TypeToRegisterSet)[RCX86_Is64To8] = Trunc64To8Registers; | 532 (*TypeToRegisterSet)[RCX86_Is64To8] = Trunc64To8Registers; |
532 (*TypeToRegisterSet)[RCX86_Is32To8] = Trunc32To8Registers; | 533 (*TypeToRegisterSet)[RCX86_Is32To8] = Trunc32To8Registers; |
533 (*TypeToRegisterSet)[RCX86_Is16To8] = Trunc16To8Registers; | 534 (*TypeToRegisterSet)[RCX86_Is16To8] = Trunc16To8Registers; |
534 (*TypeToRegisterSet)[RCX86_IsTrunc8Rcvr] = Trunc8RcvrRegisters; | 535 (*TypeToRegisterSet)[RCX86_IsTrunc8Rcvr] = Trunc8RcvrRegisters; |
535 (*TypeToRegisterSet)[RCX86_IsAhRcvr] = AhRcvrRegisters; | 536 (*TypeToRegisterSet)[RCX86_IsAhRcvr] = AhRcvrRegisters; |
536 } | 537 } |
537 | 538 |
538 static llvm::SmallBitVector | 539 static llvm::SmallBitVector |
539 getRegisterSet(TargetLowering::RegSetMask Include, | 540 getRegisterSet(const ::Ice::ClFlags & /*Flags*/, |
| 541 TargetLowering::RegSetMask Include, |
540 TargetLowering::RegSetMask Exclude) { | 542 TargetLowering::RegSetMask Exclude) { |
541 llvm::SmallBitVector Registers(RegisterSet::Reg_NUM); | 543 llvm::SmallBitVector Registers(RegisterSet::Reg_NUM); |
542 | 544 |
543 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ | 545 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ |
544 isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8, \ | 546 isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8, \ |
545 isTrunc8Rcvr, isAhRcvr, aliases) \ | 547 isTrunc8Rcvr, isAhRcvr, aliases) \ |
546 if (scratch && (Include & ::Ice::TargetLowering::RegSet_CallerSave)) \ | 548 if (scratch && (Include & ::Ice::TargetLowering::RegSet_CallerSave)) \ |
547 Registers[RegisterSet::val] = true; \ | 549 Registers[RegisterSet::val] = true; \ |
548 if (preserved && (Include & ::Ice::TargetLowering::RegSet_CalleeSave)) \ | 550 if (preserved && (Include & ::Ice::TargetLowering::RegSet_CalleeSave)) \ |
549 Registers[RegisterSet::val] = true; \ | 551 Registers[RegisterSet::val] = true; \ |
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806 DefaultSegment = -1, | 808 DefaultSegment = -1, |
807 #define X(val, name, prefix) val, | 809 #define X(val, name, prefix) val, |
808 SEG_REGX8632_TABLE | 810 SEG_REGX8632_TABLE |
809 #undef X | 811 #undef X |
810 SegReg_NUM | 812 SegReg_NUM |
811 }; | 813 }; |
812 static X86OperandMem *create(Cfg *Func, Type Ty, Variable *Base, | 814 static X86OperandMem *create(Cfg *Func, Type Ty, Variable *Base, |
813 Constant *Offset, Variable *Index = nullptr, | 815 Constant *Offset, Variable *Index = nullptr, |
814 uint16_t Shift = 0, | 816 uint16_t Shift = 0, |
815 SegmentRegisters SegmentReg = DefaultSegment, | 817 SegmentRegisters SegmentReg = DefaultSegment, |
816 bool IsPIC = false) { | 818 bool IsRebased = false) { |
817 return new (Func->allocate<X86OperandMem>()) X86OperandMem( | 819 return new (Func->allocate<X86OperandMem>()) X86OperandMem( |
818 Func, Ty, Base, Offset, Index, Shift, SegmentReg, IsPIC); | 820 Func, Ty, Base, Offset, Index, Shift, SegmentReg, IsRebased); |
| 821 } |
| 822 static X86OperandMem *create(Cfg *Func, Type Ty, Variable *Base, |
| 823 Constant *Offset, bool IsRebased) { |
| 824 constexpr Variable *NoIndex = nullptr; |
| 825 constexpr uint16_t NoShift = 0; |
| 826 return new (Func->allocate<X86OperandMem>()) X86OperandMem( |
| 827 Func, Ty, Base, Offset, NoIndex, NoShift, DefaultSegment, IsRebased); |
819 } | 828 } |
820 Variable *getBase() const { return Base; } | 829 Variable *getBase() const { return Base; } |
821 Constant *getOffset() const { return Offset; } | 830 Constant *getOffset() const { return Offset; } |
822 Variable *getIndex() const { return Index; } | 831 Variable *getIndex() const { return Index; } |
823 uint16_t getShift() const { return Shift; } | 832 uint16_t getShift() const { return Shift; } |
824 SegmentRegisters getSegmentRegister() const { return SegmentReg; } | 833 SegmentRegisters getSegmentRegister() const { return SegmentReg; } |
825 void emitSegmentOverride(Assembler *Asm) const; | 834 void emitSegmentOverride(Assembler *Asm) const; |
826 void setIsPIC() { IsPIC = true; } | 835 bool getIsRebased() const { return IsRebased; } |
827 bool getIsPIC() const { return IsPIC; } | 836 Address toAsmAddress(Assembler *Asm, const Ice::TargetLowering *Target, |
828 Address toAsmAddress(Assembler *Asm, | 837 bool LeaAddr = false) const; |
829 const Ice::TargetLowering *Target) const; | |
830 | 838 |
831 void emit(const Cfg *Func) const override; | 839 void emit(const Cfg *Func) const override; |
832 using X86Operand::dump; | 840 using X86Operand::dump; |
833 void dump(const Cfg *Func, Ostream &Str) const override; | 841 void dump(const Cfg *Func, Ostream &Str) const override; |
834 | 842 |
835 static bool classof(const Operand *Operand) { | 843 static bool classof(const Operand *Operand) { |
836 return Operand->getKind() == static_cast<OperandKind>(kMem); | 844 return Operand->getKind() == static_cast<OperandKind>(kMem); |
837 } | 845 } |
838 | 846 |
839 void setRandomized(bool R) { Randomized = R; } | 847 void setRandomized(bool R) { Randomized = R; } |
840 | 848 |
841 bool getRandomized() const { return Randomized; } | 849 bool getRandomized() const { return Randomized; } |
842 | 850 |
843 private: | 851 private: |
844 X86OperandMem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset, | 852 X86OperandMem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset, |
845 Variable *Index, uint16_t Shift, SegmentRegisters SegmentReg, | 853 Variable *Index, uint16_t Shift, SegmentRegisters SegmentReg, |
846 bool IsPIC); | 854 bool IsRebased); |
847 | 855 |
848 Variable *Base; | 856 Variable *const Base; |
849 Constant *Offset; | 857 Constant *const Offset; |
850 Variable *Index; | 858 Variable *const Index; |
851 uint16_t Shift; | 859 const uint16_t Shift; |
852 SegmentRegisters SegmentReg : 16; | 860 const SegmentRegisters SegmentReg : 16; |
853 bool IsPIC; | 861 const bool IsRebased; |
854 /// A flag to show if this memory operand is a randomized one. Randomized | 862 /// A flag to show if this memory operand is a randomized one. Randomized |
855 /// memory operands are generated in | 863 /// memory operands are generated in |
856 /// TargetX86Base::randomizeOrPoolImmediate() | 864 /// TargetX86Base::randomizeOrPoolImmediate() |
857 bool Randomized = false; | 865 bool Randomized = false; |
858 }; | 866 }; |
859 | 867 |
860 /// VariableSplit is a way to treat an f64 memory location as a pair of i32 | 868 /// VariableSplit is a way to treat an f64 memory location as a pair of i32 |
861 /// locations (Low and High). This is needed for some cases of the Bitcast | 869 /// locations (Low and High). This is needed for some cases of the Bitcast |
862 /// instruction. Since it's not possible for integer registers to access the | 870 /// instruction. Since it's not possible for integer registers to access the |
863 /// XMM registers and vice versa, the lowering forces the f64 to be spilled to | 871 /// XMM registers and vice versa, the lowering forces the f64 to be spilled to |
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954 | 962 |
955 static uint8_t InstSegmentPrefixes[]; | 963 static uint8_t InstSegmentPrefixes[]; |
956 }; | 964 }; |
957 | 965 |
958 using Traits = ::Ice::X8632::TargetX8632Traits; | 966 using Traits = ::Ice::X8632::TargetX8632Traits; |
959 } // end of namespace X8632 | 967 } // end of namespace X8632 |
960 | 968 |
961 } // end of namespace Ice | 969 } // end of namespace Ice |
962 | 970 |
963 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H | 971 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H |
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