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1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// | 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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123 TargetX86Base<X8632::Traits>::Traits::FK_Abs; | 123 TargetX86Base<X8632::Traits>::Traits::FK_Abs; |
124 | 124 |
125 //------------------------------------------------------------------------------ | 125 //------------------------------------------------------------------------------ |
126 // __ ______ __ __ ______ ______ __ __ __ ______ | 126 // __ ______ __ __ ______ ______ __ __ __ ______ |
127 // /\ \ /\ __ \/\ \ _ \ \/\ ___\/\ == \/\ \/\ "-.\ \/\ ___\ | 127 // /\ \ /\ __ \/\ \ _ \ \/\ ___\/\ == \/\ \/\ "-.\ \/\ ___\ |
128 // \ \ \___\ \ \/\ \ \ \/ ".\ \ \ __\\ \ __<\ \ \ \ \-. \ \ \__ \ | 128 // \ \ \___\ \ \/\ \ \ \/ ".\ \ \ __\\ \ __<\ \ \ \ \-. \ \ \__ \ |
129 // \ \_____\ \_____\ \__/".~\_\ \_____\ \_\ \_\ \_\ \_\\"\_\ \_____\ | 129 // \ \_____\ \_____\ \__/".~\_\ \_____\ \_\ \_\ \_\ \_\\"\_\ \_____\ |
130 // \/_____/\/_____/\/_/ \/_/\/_____/\/_/ /_/\/_/\/_/ \/_/\/_____/ | 130 // \/_____/\/_____/\/_/ \/_/\/_____/\/_/ /_/\/_/\/_/ \/_/\/_____/ |
131 // | 131 // |
132 //------------------------------------------------------------------------------ | 132 //------------------------------------------------------------------------------ |
| 133 void TargetX8632::_add_sp(Operand *Adjustment) { |
| 134 Variable *esp = getPhysicalRegister(Traits::RegisterSet::Reg_esp); |
| 135 _add(esp, Adjustment); |
| 136 } |
| 137 |
| 138 void TargetX8632::_mov_sp(Operand *NewValue) { |
| 139 Variable *esp = getPhysicalRegister(Traits::RegisterSet::Reg_esp); |
| 140 _redefined(_mov(esp, NewValue)); |
| 141 } |
| 142 |
| 143 void TargetX8632::_sub_sp(Operand *Adjustment) { |
| 144 Variable *esp = getPhysicalRegister(Traits::RegisterSet::Reg_esp); |
| 145 _sub(esp, Adjustment); |
| 146 } |
| 147 |
| 148 void TargetX8632::lowerIndirectJump(Variable *JumpTarget) { |
| 149 if (NeedSandboxing) { |
| 150 _bundle_lock(); |
| 151 const SizeT BundleSize = |
| 152 1 << Func->getAssembler<>()->getBundleAlignLog2Bytes(); |
| 153 _and(JumpTarget, Ctx->getConstantInt32(~(BundleSize - 1))); |
| 154 } |
| 155 _jmp(JumpTarget); |
| 156 if (NeedSandboxing) |
| 157 _bundle_unlock(); |
| 158 } |
| 159 |
133 void TargetX8632::lowerCall(const InstCall *Instr) { | 160 void TargetX8632::lowerCall(const InstCall *Instr) { |
134 // x86-32 calling convention: | 161 // x86-32 calling convention: |
135 // | 162 // |
136 // * At the point before the call, the stack must be aligned to 16 bytes. | 163 // * At the point before the call, the stack must be aligned to 16 bytes. |
137 // | 164 // |
138 // * The first four arguments of vector type, regardless of their position | 165 // * The first four arguments of vector type, regardless of their position |
139 // relative to the other arguments in the argument list, are placed in | 166 // relative to the other arguments in the argument list, are placed in |
140 // registers xmm0 - xmm3. | 167 // registers xmm0 - xmm3. |
141 // | 168 // |
142 // * Other arguments are pushed onto the stack in right-to-left order, such | 169 // * Other arguments are pushed onto the stack in right-to-left order, such |
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246 case IceType_v16i8: | 273 case IceType_v16i8: |
247 case IceType_v8i16: | 274 case IceType_v8i16: |
248 case IceType_v4i32: | 275 case IceType_v4i32: |
249 case IceType_v4f32: | 276 case IceType_v4f32: |
250 ReturnReg = makeReg(DestTy, Traits::RegisterSet::Reg_xmm0); | 277 ReturnReg = makeReg(DestTy, Traits::RegisterSet::Reg_xmm0); |
251 break; | 278 break; |
252 } | 279 } |
253 } | 280 } |
254 Operand *CallTarget = | 281 Operand *CallTarget = |
255 legalize(Instr->getCallTarget(), Legal_Reg | Legal_Imm | Legal_AddrAbs); | 282 legalize(Instr->getCallTarget(), Legal_Reg | Legal_Imm | Legal_AddrAbs); |
256 const bool NeedSandboxing = Ctx->getFlags().getUseSandboxing(); | |
257 if (NeedSandboxing) { | 283 if (NeedSandboxing) { |
258 if (llvm::isa<Constant>(CallTarget)) { | 284 if (llvm::isa<Constant>(CallTarget)) { |
259 _bundle_lock(InstBundleLock::Opt_AlignToEnd); | 285 _bundle_lock(InstBundleLock::Opt_AlignToEnd); |
260 } else { | 286 } else { |
261 Variable *CallTargetVar = nullptr; | 287 Variable *CallTargetVar = nullptr; |
262 _mov(CallTargetVar, CallTarget); | 288 _mov(CallTargetVar, CallTarget); |
263 _bundle_lock(InstBundleLock::Opt_AlignToEnd); | 289 _bundle_lock(InstBundleLock::Opt_AlignToEnd); |
264 const SizeT BundleSize = | 290 const SizeT BundleSize = |
265 1 << Func->getAssembler<>()->getBundleAlignLog2Bytes(); | 291 1 << Func->getAssembler<>()->getBundleAlignLog2Bytes(); |
266 _and(CallTargetVar, Ctx->getConstantInt32(~(BundleSize - 1))); | 292 _and(CallTargetVar, Ctx->getConstantInt32(~(BundleSize - 1))); |
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716 for (SizeT i = 0; i < Popped.size(); ++i) { | 742 for (SizeT i = 0; i < Popped.size(); ++i) { |
717 SizeT j = Popped.size() - i - 1; | 743 SizeT j = Popped.size() - i - 1; |
718 SizeT Canonical = Traits::getBaseReg(j); | 744 SizeT Canonical = Traits::getBaseReg(j); |
719 if (j == Traits::RegisterSet::Reg_ebp && IsEbpBasedFrame) | 745 if (j == Traits::RegisterSet::Reg_ebp && IsEbpBasedFrame) |
720 continue; | 746 continue; |
721 if (Popped[j]) { | 747 if (Popped[j]) { |
722 _pop(getPhysicalRegister(Canonical)); | 748 _pop(getPhysicalRegister(Canonical)); |
723 } | 749 } |
724 } | 750 } |
725 | 751 |
726 if (!Ctx->getFlags().getUseSandboxing()) | 752 if (!NeedSandboxing) |
727 return; | 753 return; |
728 // Change the original ret instruction into a sandboxed return sequence. | 754 // Change the original ret instruction into a sandboxed return sequence. |
729 // t:ecx = pop | 755 // t:ecx = pop |
730 // bundle_lock | 756 // bundle_lock |
731 // and t, ~31 | 757 // and t, ~31 |
732 // jmp *t | 758 // jmp *t |
733 // bundle_unlock | 759 // bundle_unlock |
734 // FakeUse <original_ret_operand> | 760 // FakeUse <original_ret_operand> |
735 Variable *T_ecx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ecx); | 761 Variable *T_ecx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ecx); |
736 _pop(T_ecx); | 762 _pop(T_ecx); |
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1063 #define X(tag, sizeLog2, align, elts, elty, str) \ | 1089 #define X(tag, sizeLog2, align, elts, elty, str) \ |
1064 static_assert(_table1_##tag == _table2_##tag, \ | 1090 static_assert(_table1_##tag == _table2_##tag, \ |
1065 "Inconsistency between ICETYPEX8632_TABLE and ICETYPE_TABLE"); | 1091 "Inconsistency between ICETYPEX8632_TABLE and ICETYPE_TABLE"); |
1066 ICETYPE_TABLE | 1092 ICETYPE_TABLE |
1067 #undef X | 1093 #undef X |
1068 } // end of namespace dummy3 | 1094 } // end of namespace dummy3 |
1069 } // end of anonymous namespace | 1095 } // end of anonymous namespace |
1070 | 1096 |
1071 } // end of namespace X8632 | 1097 } // end of namespace X8632 |
1072 } // end of namespace Ice | 1098 } // end of namespace Ice |
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