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Issue 1559243002: Suzero. X8664. NaCl Sandboxing. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fixes filetype=asm; addresses comments. Created 4 years, 11 months ago
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1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -*- C++ -*-===// 1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of lowered x86-64 instructions in the 10 // This file defines properties of lowered x86-64 instructions in the
(...skipping 12 matching lines...) Expand all
23 // Scratch XMMs: xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, 23 // Scratch XMMs: xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
24 // xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 24 // xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15
25 // Key to table columns: 25 // Key to table columns:
26 // val: Enum value, when a specific register is needed during lowering. 26 // val: Enum value, when a specific register is needed during lowering.
27 // encode: Encoding in the integrated assembler. 27 // encode: Encoding in the integrated assembler.
28 // name: Name used for the external assembler. 28 // name: Name used for the external assembler.
29 // scratch: Scratch (caller-save) register. 29 // scratch: Scratch (caller-save) register.
30 // preserved: Preserved (callee-save) register. 30 // preserved: Preserved (callee-save) register.
31 // stackptr: This register is used as the stack pointer. 31 // stackptr: This register is used as the stack pointer.
32 // frameptr: This register is used as the frame pointer if needed. 32 // frameptr: This register is used as the frame pointer if needed.
33 // sboxres: This register is reserved in sandboxing.
33 // isGPR: This is a GPR (integer-type). 34 // isGPR: This is a GPR (integer-type).
34 // is64: This is a 64-bit GPR. 35 // is64: This is a 64-bit GPR.
35 // is32: This is a 32-bit GPR. 36 // is32: This is a 32-bit GPR.
36 // is16: This is a 16-bit GPR. 37 // is16: This is a 16-bit GPR.
37 // is8: This is an 8-bit GPR. 38 // is8: This is an 8-bit GPR.
38 // isXmm: This is an XMM register for FP and vector ops. 39 // isXmm: This is an XMM register for FP and vector ops.
39 // is64To8: A 64-bit GPR truncable to 8-bit. 40 // is64To8: A 64-bit GPR truncable to 8-bit.
40 // is32To8: A 32-bit GPR truncable to 8-bit. 41 // is32To8: A 32-bit GPR truncable to 8-bit.
41 // is16To8: A 16-bit GPR truncable to 8-bit. 42 // is16To8: A 16-bit GPR truncable to 8-bit.
42 // isTrunc8Rcvr: An 8-bit GPR that a wider GPR trivially truncates to. 43 // isTrunc8Rcvr: An 8-bit GPR that a wider GPR trivially truncates to.
43 // isAhRcvr: An 8-bit GPR that register "ah" can be assigned to. 44 // isAhRcvr: An 8-bit GPR that register "ah" can be assigned to.
44 // aliases: List of register aliases, which need not include this register. 45 // aliases: List of register aliases, which need not include this register.
45 #define REGX8664_BYTEREG_TABLE \ 46 #define REGX8664_BYTEREG_TABLE \
46 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \ 47 /* val, encode, name, base, scratch,preserved,stackptr,frameptr,sboxres, \
47 isGPR,is64,is32,is16,is8, isXmm, \ 48 isGPR,is64,is32,is16,is8, isXmm, \
48 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \ 49 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
49 /* 8-bit registers */ \ 50 /* 8-bit registers */ \
50 X(Reg_al, 0, "al", Reg_rax, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \ 51 X(Reg_al, 0, "al", Reg_rax, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
51 REGLIST3(RegX8664, rax, eax, ax)) \ 52 REGLIST3(RegX8664, rax, eax, ax)) \
52 X(Reg_cl, 1, "cl", Reg_rcx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \ 53 X(Reg_cl, 1, "cl", Reg_rcx, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
53 REGLIST3(RegX8664, rcx, ecx, cx)) \ 54 REGLIST3(RegX8664, rcx, ecx, cx)) \
54 X(Reg_dl, 2, "dl", Reg_rdx, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \ 55 X(Reg_dl, 2, "dl", Reg_rdx, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
55 REGLIST3(RegX8664, rdx, edx, dx)) \ 56 REGLIST3(RegX8664, rdx, edx, dx)) \
56 X(Reg_bl, 3, "bl", Reg_rbx, 0,1,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \ 57 X(Reg_bl, 3, "bl", Reg_rbx, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,1, \
57 REGLIST3(RegX8664, rbx, ebx, bx)) \ 58 REGLIST3(RegX8664, rbx, ebx, bx)) \
58 X(Reg_spl, 4, "spl", Reg_rsp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \ 59 X(Reg_spl, 4, "spl", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
59 REGLIST3(RegX8664, rsp, esp, sp)) \ 60 REGLIST3(RegX8664, rsp, esp, sp)) \
60 X(Reg_bpl, 5, "bpl", Reg_rbp, 0,1,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \ 61 X(Reg_bpl, 5, "bpl", Reg_rbp, 0,1,0,1,1, 1,0,0,0,1, 0, 0,0,0,1,0, \
61 REGLIST3(RegX8664, rbp, ebp, bp)) \ 62 REGLIST3(RegX8664, rbp, ebp, bp)) \
62 X(Reg_sil, 6, "sil", Reg_rsi, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 63 X(Reg_sil, 6, "sil", Reg_rsi, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
63 REGLIST3(RegX8664, rsi, esi, si)) \ 64 REGLIST3(RegX8664, rsi, esi, si)) \
64 X(Reg_dil, 7, "dil", Reg_rdi, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 65 X(Reg_dil, 7, "dil", Reg_rdi, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
65 REGLIST3(RegX8664, rdi, edi, di)) \ 66 REGLIST3(RegX8664, rdi, edi, di)) \
66 X(Reg_r8l, 8, "r8b", Reg_r8, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 67 X(Reg_r8l, 8, "r8b", Reg_r8, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
67 REGLIST3(RegX8664, r8, r8d, r8w)) \ 68 REGLIST3(RegX8664, r8, r8d, r8w)) \
68 X(Reg_r9l, 9, "r9b", Reg_r9, 1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \ 69 X(Reg_r9l, 9, "r9b", Reg_r9, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
69 REGLIST3(RegX8664, r9, r9d, r9w)) \ 70 REGLIST3(RegX8664, r9, r9d, r9w)) \
70 X(Reg_r10l, 10, "r10b", Reg_r10, 1,0,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \ 71 X(Reg_r10l, 10, "r10b", Reg_r10, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
71 REGLIST3(RegX8664, r10, r10d, r10w)) \ 72 REGLIST3(RegX8664, r10, r10d, r10w)) \
72 X(Reg_r11l, 11, "r11b", Reg_r11, 1,0,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \ 73 X(Reg_r11l, 11, "r11b", Reg_r11, 1,0,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
73 REGLIST3(RegX8664, r11, r11d, r11w)) \ 74 REGLIST3(RegX8664, r11, r11d, r11w)) \
74 X(Reg_r12l, 12, "r12b", Reg_r12, 0,1,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \ 75 X(Reg_r12l, 12, "r12b", Reg_r12, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
75 REGLIST3(RegX8664, r12, r12d, r12w)) \ 76 REGLIST3(RegX8664, r12, r12d, r12w)) \
76 X(Reg_r13l, 13, "r13b", Reg_r13, 0,1,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \ 77 X(Reg_r13l, 13, "r13b", Reg_r13, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
77 REGLIST3(RegX8664, r13, r13d, r13w)) \ 78 REGLIST3(RegX8664, r13, r13d, r13w)) \
78 X(Reg_r14l, 14, "r14b", Reg_r14, 0,1,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \ 79 X(Reg_r14l, 14, "r14b", Reg_r14, 0,1,0,0,0, 1,0,0,0,1, 0, 0,0,0,1,0, \
79 REGLIST3(RegX8664, r14, r14d, r14w)) \ 80 REGLIST3(RegX8664, r14, r14d, r14w)) \
80 X(Reg_r15l, 15, "r15b", Reg_r15, 0,1,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \ 81 X(Reg_r15l, 15, "r15b", Reg_r15, 0,1,0,0,1, 1,0,0,0,1, 0, 0,0,0,1,0, \
81 REGLIST3(RegX8664, r15, r15d, r15w)) \ 82 REGLIST3(RegX8664, r15, r15d, r15w)) \
82 /* High 8-bit registers. None are allowed for register allocation. */ \ 83 /* High 8-bit registers. None are allowed for register allocation. */ \
83 X(Reg_ah, 4, "ah", Reg_rax, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \ 84 X(Reg_ah, 4, "ah", Reg_rax, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
84 REGLIST3(RegX8664, rax, eax, ax)) \ 85 REGLIST3(RegX8664, rax, eax, ax)) \
85 X(Reg_ch, 5, "ch", Reg_rcx, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \ 86 X(Reg_ch, 5, "ch", Reg_rcx, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
86 REGLIST3(RegX8664, rcx, ecx, cx)) \ 87 REGLIST3(RegX8664, rcx, ecx, cx)) \
87 X(Reg_dh, 6, "dh", Reg_rdx, 1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \ 88 X(Reg_dh, 6, "dh", Reg_rdx, 1,0,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
88 REGLIST3(RegX8664, rdx, edx, dx)) \ 89 REGLIST3(RegX8664, rdx, edx, dx)) \
89 X(Reg_bh, 7, "bh", Reg_rbx, 0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \ 90 X(Reg_bh, 7, "bh", Reg_rbx, 0,1,0,0,0, 1,0,0,0,0, 0, 0,0,0,0,1, \
90 REGLIST3(RegX8664, rbx, ebx, bx)) \ 91 REGLIST3(RegX8664, rbx, ebx, bx)) \
91 /* End of 8-bit register set */ 92 /* End of 8-bit register set */
92 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, 93 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
93 // isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8, 94 // sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8,
94 // isTrunc8Rcvr, isAhRcvr, aliases) 95 // is16To8, isTrunc8Rcvr, isAhRcvr, aliases)
95 96
96 #define REGX8664_GPR_TABLE \ 97 #define REGX8664_GPR_TABLE \
97 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \ 98 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \
98 isGPR,is64,is32,is16,is8, isXmm, \ 99 isGPR,is64,is32,is16,is8, isXmm, \
99 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \ 100 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
100 /* 64-bit registers */ \ 101 /* 64-bit registers */ \
101 X(Reg_rax, 0, "rax", Reg_rax, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 102 X(Reg_rax, 0, "rax", Reg_rax, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
102 REGLIST4(RegX8664, eax, ax, al, ah)) \ 103 REGLIST4(RegX8664, eax, ax, al, ah)) \
103 X(Reg_rcx, 1, "rcx", Reg_rcx, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 104 X(Reg_rcx, 1, "rcx", Reg_rcx, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
104 REGLIST4(RegX8664, ecx, cx, cl, ch)) \ 105 REGLIST4(RegX8664, ecx, cx, cl, ch)) \
105 X(Reg_rdx, 2, "rdx", Reg_rdx, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 106 X(Reg_rdx, 2, "rdx", Reg_rdx, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
106 REGLIST4(RegX8664, edx, dx, dl, dh)) \ 107 REGLIST4(RegX8664, edx, dx, dl, dh)) \
107 X(Reg_rbx, 3, "rbx", Reg_rbx, 0,1,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 108 X(Reg_rbx, 3, "rbx", Reg_rbx, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
108 REGLIST4(RegX8664, ebx, bx, bl, bh)) \ 109 REGLIST4(RegX8664, ebx, bx, bl, bh)) \
109 X(Reg_rsp, 4, "rsp", Reg_rsp, 0,0,1,0, 1,0,0,0,0, 0, 1,0,0,0,0, \ 110 X(Reg_rsp, 4, "rsp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 1,0,0,0,0, \
110 REGLIST3(RegX8664, esp, sp, spl)) \ 111 REGLIST3(RegX8664, esp, sp, spl)) \
111 X(Reg_rbp, 5, "rbp", Reg_rbp, 0,1,0,1, 1,1,0,0,0, 0, 1,0,0,0,0, \ 112 X(Reg_rbp, 5, "rbp", Reg_rbp, 0,1,0,1,1, 1,1,0,0,0, 0, 1,0,0,0,0, \
112 REGLIST3(RegX8664, ebp, bp, bpl)) \ 113 REGLIST3(RegX8664, ebp, bp, bpl)) \
113 X(Reg_rsi, 6, "rsi", Reg_rsi, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 114 X(Reg_rsi, 6, "rsi", Reg_rsi, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
114 REGLIST3(RegX8664, esi, si, sil)) \ 115 REGLIST3(RegX8664, esi, si, sil)) \
115 X(Reg_rdi, 7, "rdi", Reg_rdi, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 116 X(Reg_rdi, 7, "rdi", Reg_rdi, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
116 REGLIST3(RegX8664, edi, di, dil)) \ 117 REGLIST3(RegX8664, edi, di, dil)) \
117 X(Reg_r8, 8, "r8", Reg_r8, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 118 X(Reg_r8, 8, "r8", Reg_r8, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
118 REGLIST3(RegX8664, r8d, r8w, r8l)) \ 119 REGLIST3(RegX8664, r8d, r8w, r8l)) \
119 X(Reg_r9, 9, "r9", Reg_r9, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 120 X(Reg_r9, 9, "r9", Reg_r9, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
120 REGLIST3(RegX8664, r9d, r9w, r9l)) \ 121 REGLIST3(RegX8664, r9d, r9w, r9l)) \
121 X(Reg_r10, 10, "r10", Reg_r10, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 122 X(Reg_r10, 10, "r10", Reg_r10, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
122 REGLIST3(RegX8664, r10d, r10w, r10l)) \ 123 REGLIST3(RegX8664, r10d, r10w, r10l)) \
123 X(Reg_r11, 11, "r11", Reg_r11, 1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 124 X(Reg_r11, 11, "r11", Reg_r11, 1,0,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
124 REGLIST3(RegX8664, r11d, r11w, r11l)) \ 125 REGLIST3(RegX8664, r11d, r11w, r11l)) \
125 X(Reg_r12, 12, "r12", Reg_r12, 0,1,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 126 X(Reg_r12, 12, "r12", Reg_r12, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
126 REGLIST3(RegX8664, r12d, r12w, r12l)) \ 127 REGLIST3(RegX8664, r12d, r12w, r12l)) \
127 X(Reg_r13, 13, "r13", Reg_r13, 0,1,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 128 X(Reg_r13, 13, "r13", Reg_r13, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
128 REGLIST3(RegX8664, r13d, r13w, r13l)) \ 129 REGLIST3(RegX8664, r13d, r13w, r13l)) \
129 X(Reg_r14, 14, "r14", Reg_r14, 0,1,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 130 X(Reg_r14, 14, "r14", Reg_r14, 0,1,0,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \
130 REGLIST3(RegX8664, r14d, r14w, r14l)) \ 131 REGLIST3(RegX8664, r14d, r14w, r14l)) \
131 X(Reg_r15, 15, "r15", Reg_r15, 0,1,0,0, 1,1,0,0,0, 0, 1,0,0,0,0, \ 132 X(Reg_r15, 15, "r15", Reg_r15, 0,1,0,0,1, 1,1,0,0,0, 0, 1,0,0,0,0, \
132 REGLIST3(RegX8664, r15d, r15w, r15l)) \ 133 REGLIST3(RegX8664, r15d, r15w, r15l)) \
133 /* 32-bit registers */ \ 134 /* 32-bit registers */ \
134 X(Reg_eax, 0, "eax", Reg_rax, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 135 X(Reg_eax, 0, "eax", Reg_rax, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
135 REGLIST4(RegX8664, rax, ax, al, ah)) \ 136 REGLIST4(RegX8664, rax, ax, al, ah)) \
136 X(Reg_ecx, 1, "ecx", Reg_rcx, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 137 X(Reg_ecx, 1, "ecx", Reg_rcx, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
137 REGLIST4(RegX8664, rcx, cx, cl, ch)) \ 138 REGLIST4(RegX8664, rcx, cx, cl, ch)) \
138 X(Reg_edx, 2, "edx", Reg_rdx, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 139 X(Reg_edx, 2, "edx", Reg_rdx, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
139 REGLIST4(RegX8664, rdx, dx, dl, dh)) \ 140 REGLIST4(RegX8664, rdx, dx, dl, dh)) \
140 X(Reg_ebx, 3, "ebx", Reg_rbx, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 141 X(Reg_ebx, 3, "ebx", Reg_rbx, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
141 REGLIST4(RegX8664, rbx, bx, bl, bh)) \ 142 REGLIST4(RegX8664, rbx, bx, bl, bh)) \
142 X(Reg_esp, 4, "esp", Reg_rsp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \ 143 X(Reg_esp, 4, "esp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
143 REGLIST3(RegX8664, rsp, sp, spl)) \ 144 REGLIST3(RegX8664, rsp, sp, spl)) \
144 X(Reg_ebp, 5, "ebp", Reg_rbp, 0,1,0,1, 1,0,1,0,0, 0, 0,1,0,0,0, \ 145 X(Reg_ebp, 5, "ebp", Reg_rbp, 0,1,0,1,1, 1,0,1,0,0, 0, 0,1,0,0,0, \
145 REGLIST3(RegX8664, rbp, bp, bpl)) \ 146 REGLIST3(RegX8664, rbp, bp, bpl)) \
146 X(Reg_esi, 6, "esi", Reg_rsi, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 147 X(Reg_esi, 6, "esi", Reg_rsi, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
147 REGLIST3(RegX8664, rsi, si, sil)) \ 148 REGLIST3(RegX8664, rsi, si, sil)) \
148 X(Reg_edi, 7, "edi", Reg_rdi, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 149 X(Reg_edi, 7, "edi", Reg_rdi, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
149 REGLIST3(RegX8664, rdi, di, dil)) \ 150 REGLIST3(RegX8664, rdi, di, dil)) \
150 X(Reg_r8d, 8, "r8d", Reg_r8, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 151 X(Reg_r8d, 8, "r8d", Reg_r8, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
151 REGLIST3(RegX8664, r8, r8w, r8l)) \ 152 REGLIST3(RegX8664, r8, r8w, r8l)) \
152 X(Reg_r9d, 9, "r9d", Reg_r9, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 153 X(Reg_r9d, 9, "r9d", Reg_r9, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
153 REGLIST3(RegX8664, r9, r9w, r9l)) \ 154 REGLIST3(RegX8664, r9, r9w, r9l)) \
154 X(Reg_r10d, 10, "r10d", Reg_r10, 1,0,0,1, 1,0,1,0,0, 0, 0,1,0,0,0, \ 155 X(Reg_r10d, 10, "r10d", Reg_r10, 1,0,0,1,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
155 REGLIST3(RegX8664, r10, r10w, r10l)) \ 156 REGLIST3(RegX8664, r10, r10w, r10l)) \
156 X(Reg_r11d, 11, "r11d", Reg_r11, 1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 157 X(Reg_r11d, 11, "r11d", Reg_r11, 1,0,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
157 REGLIST3(RegX8664, r11, r11w, r11l)) \ 158 REGLIST3(RegX8664, r11, r11w, r11l)) \
158 X(Reg_r12d, 12, "r12d", Reg_r12, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 159 X(Reg_r12d, 12, "r12d", Reg_r12, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
159 REGLIST3(RegX8664, r12, r12w, r12l)) \ 160 REGLIST3(RegX8664, r12, r12w, r12l)) \
160 X(Reg_r13d, 13, "r13d", Reg_r13, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 161 X(Reg_r13d, 13, "r13d", Reg_r13, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
161 REGLIST3(RegX8664, r13, r13w, r13l)) \ 162 REGLIST3(RegX8664, r13, r13w, r13l)) \
162 X(Reg_r14d, 14, "r14d", Reg_r14, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 163 X(Reg_r14d, 14, "r14d", Reg_r14, 0,1,0,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \
163 REGLIST3(RegX8664, r14, r14w, r14l)) \ 164 REGLIST3(RegX8664, r14, r14w, r14l)) \
164 X(Reg_r15d, 15, "r15d", Reg_r15, 0,1,0,0, 1,0,1,0,0, 0, 0,1,0,0,0, \ 165 X(Reg_r15d, 15, "r15d", Reg_r15, 0,1,0,0,1, 1,0,1,0,0, 0, 0,1,0,0,0, \
165 REGLIST3(RegX8664, r15, r15w, r15l)) \ 166 REGLIST3(RegX8664, r15, r15w, r15l)) \
166 /* 16-bit registers */ \ 167 /* 16-bit registers */ \
167 X(Reg_ax, 0, "ax", Reg_rax, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 168 X(Reg_ax, 0, "ax", Reg_rax, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
168 REGLIST4(RegX8664, rax, eax, al, ah)) \ 169 REGLIST4(RegX8664, rax, eax, al, ah)) \
169 X(Reg_cx, 1, "cx", Reg_rcx, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 170 X(Reg_cx, 1, "cx", Reg_rcx, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
170 REGLIST4(RegX8664, rcx, ecx, cl, ch)) \ 171 REGLIST4(RegX8664, rcx, ecx, cl, ch)) \
171 X(Reg_dx, 2, "dx", Reg_rdx, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 172 X(Reg_dx, 2, "dx", Reg_rdx, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
172 REGLIST4(RegX8664, rdx, edx, dl, dh)) \ 173 REGLIST4(RegX8664, rdx, edx, dl, dh)) \
173 X(Reg_bx, 3, "bx", Reg_rbx, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 174 X(Reg_bx, 3, "bx", Reg_rbx, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
174 REGLIST4(RegX8664, rbx, ebx, bl, bh)) \ 175 REGLIST4(RegX8664, rbx, ebx, bl, bh)) \
175 X(Reg_sp, 4, "sp", Reg_rsp, 0,0,1,0, 1,0,0,0,0, 0, 0,0,0,0,0, \ 176 X(Reg_sp, 4, "sp", Reg_rsp, 0,0,1,0,0, 1,0,0,0,0, 0, 0,0,0,0,0, \
176 REGLIST3(RegX8664, rsp, esp, spl)) \ 177 REGLIST3(RegX8664, rsp, esp, spl)) \
177 X(Reg_bp, 5, "bp", Reg_rbp, 0,1,0,1, 1,0,0,1,0, 0, 0,0,1,0,0, \ 178 X(Reg_bp, 5, "bp", Reg_rbp, 0,1,0,1,1, 1,0,0,1,0, 0, 0,0,1,0,0, \
178 REGLIST3(RegX8664, rbp, ebp, bpl)) \ 179 REGLIST3(RegX8664, rbp, ebp, bpl)) \
179 X(Reg_si, 6, "si", Reg_rsi, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 180 X(Reg_si, 6, "si", Reg_rsi, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
180 REGLIST3(RegX8664, rsi, esi, sil)) \ 181 REGLIST3(RegX8664, rsi, esi, sil)) \
181 X(Reg_di, 7, "di", Reg_rdi, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 182 X(Reg_di, 7, "di", Reg_rdi, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
182 REGLIST3(RegX8664, rdi, edi, dil)) \ 183 REGLIST3(RegX8664, rdi, edi, dil)) \
183 X(Reg_r8w, 8, "r8w", Reg_r8, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 184 X(Reg_r8w, 8, "r8w", Reg_r8, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
184 REGLIST3(RegX8664, r8, r8d, r8l)) \ 185 REGLIST3(RegX8664, r8, r8d, r8l)) \
185 X(Reg_r9w, 9, "r9w", Reg_r9, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 186 X(Reg_r9w, 9, "r9w", Reg_r9, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
186 REGLIST3(RegX8664, r9, r9d, r9l)) \ 187 REGLIST3(RegX8664, r9, r9d, r9l)) \
187 X(Reg_r10w, 10, "r10w", Reg_r10, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 188 X(Reg_r10w, 10, "r10w", Reg_r10, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
188 REGLIST3(RegX8664, r10, r10d, r10l)) \ 189 REGLIST3(RegX8664, r10, r10d, r10l)) \
189 X(Reg_r11w, 11, "r11w", Reg_r11, 1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 190 X(Reg_r11w, 11, "r11w", Reg_r11, 1,0,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
190 REGLIST3(RegX8664, r11, r11d, r11l)) \ 191 REGLIST3(RegX8664, r11, r11d, r11l)) \
191 X(Reg_r12w, 12, "r12w", Reg_r12, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 192 X(Reg_r12w, 12, "r12w", Reg_r12, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
192 REGLIST3(RegX8664, r12, r12d, r12l)) \ 193 REGLIST3(RegX8664, r12, r12d, r12l)) \
193 X(Reg_r13w, 13, "r13w", Reg_r13, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 194 X(Reg_r13w, 13, "r13w", Reg_r13, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
194 REGLIST3(RegX8664, r13, r13d, r13l)) \ 195 REGLIST3(RegX8664, r13, r13d, r13l)) \
195 X(Reg_r14w, 14, "r14w", Reg_r14, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 196 X(Reg_r14w, 14, "r14w", Reg_r14, 0,1,0,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \
196 REGLIST3(RegX8664, r14, r14d, r14l)) \ 197 REGLIST3(RegX8664, r14, r14d, r14l)) \
197 X(Reg_r15w, 15, "r15w", Reg_r15, 0,1,0,0, 1,0,0,1,0, 0, 0,0,1,0,0, \ 198 X(Reg_r15w, 15, "r15w", Reg_r15, 0,1,0,0,1, 1,0,0,1,0, 0, 0,0,1,0,0, \
198 REGLIST3(RegX8664, r15, r15d, r15l)) \ 199 REGLIST3(RegX8664, r15, r15d, r15l)) \
199 /* 8-bit registers */ \ 200 /* 8-bit registers */ \
200 REGX8664_BYTEREG_TABLE \ 201 REGX8664_BYTEREG_TABLE \
201 /* End of GPR register set */ 202 /* End of GPR register set */
202 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, 203 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
203 // isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8, 204 // sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8,
204 // isTrunc8Rcvr, isAhRcvr, aliases) 205 // is16To8, isTrunc8Rcvr, isAhRcvr, aliases)
205 206
206 // Note: It would be more appropriate to list the xmm register aliases as 207 // Note: It would be more appropriate to list the xmm register aliases as
207 // REGLIST0(), but the corresponding empty initializer gives a syntax error, so 208 // REGLIST0(), but the corresponding empty initializer gives a syntax error, so
208 // we use REGLIST1() to redundantly assign the register itself as an alias. 209 // we use REGLIST1() to redundantly assign the register itself as an alias.
209 #define REGX8664_XMM_TABLE \ 210 #define REGX8664_XMM_TABLE \
210 /* val, encode, name, base, scratch,preserved,stackptr,frameptr, \ 211 /* val, encode, name, base, scratch,preserved,stackptr,frameptr,sboxres, \
211 isGPR,is64,is32,is16,is8, isXmm, \ 212 isGPR,is64,is32,is16,is8, isXmm, \
212 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \ 213 is64To8,is32To8,is16To8,isTrunc8Rcvr,isAhRcvr, aliases */ \
213 /* xmm registers */ \ 214 /* xmm registers */ \
214 X(Reg_xmm0, 0, "xmm0", Reg_xmm0, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 215 X(Reg_xmm0, 0, "xmm0", Reg_xmm0, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
215 NO_ALIASES()) \ 216 NO_ALIASES()) \
216 X(Reg_xmm1, 1, "xmm1", Reg_xmm1, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 217 X(Reg_xmm1, 1, "xmm1", Reg_xmm1, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
217 NO_ALIASES()) \ 218 NO_ALIASES()) \
218 X(Reg_xmm2, 2, "xmm2", Reg_xmm2, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 219 X(Reg_xmm2, 2, "xmm2", Reg_xmm2, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
219 NO_ALIASES()) \ 220 NO_ALIASES()) \
220 X(Reg_xmm3, 3, "xmm3", Reg_xmm3, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 221 X(Reg_xmm3, 3, "xmm3", Reg_xmm3, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
221 NO_ALIASES()) \ 222 NO_ALIASES()) \
222 X(Reg_xmm4, 4, "xmm4", Reg_xmm4, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 223 X(Reg_xmm4, 4, "xmm4", Reg_xmm4, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
223 NO_ALIASES()) \ 224 NO_ALIASES()) \
224 X(Reg_xmm5, 5, "xmm5", Reg_xmm5, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 225 X(Reg_xmm5, 5, "xmm5", Reg_xmm5, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
225 NO_ALIASES()) \ 226 NO_ALIASES()) \
226 X(Reg_xmm6, 6, "xmm6", Reg_xmm6, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 227 X(Reg_xmm6, 6, "xmm6", Reg_xmm6, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
227 NO_ALIASES()) \ 228 NO_ALIASES()) \
228 X(Reg_xmm7, 7, "xmm7", Reg_xmm7, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 229 X(Reg_xmm7, 7, "xmm7", Reg_xmm7, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
229 NO_ALIASES()) \ 230 NO_ALIASES()) \
230 X(Reg_xmm8, 8, "xmm8", Reg_xmm8, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 231 X(Reg_xmm8, 8, "xmm8", Reg_xmm8, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
231 NO_ALIASES()) \ 232 NO_ALIASES()) \
232 X(Reg_xmm9, 9, "xmm9", Reg_xmm9, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 233 X(Reg_xmm9, 9, "xmm9", Reg_xmm9, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
233 NO_ALIASES()) \ 234 NO_ALIASES()) \
234 X(Reg_xmm10, 10, "xmm10", Reg_xmm10, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 235 X(Reg_xmm10, 10, "xmm10", Reg_xmm10, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
235 NO_ALIASES()) \ 236 NO_ALIASES()) \
236 X(Reg_xmm11, 11, "xmm11", Reg_xmm11, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 237 X(Reg_xmm11, 11, "xmm11", Reg_xmm11, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
237 NO_ALIASES()) \ 238 NO_ALIASES()) \
238 X(Reg_xmm12, 12, "xmm12", Reg_xmm12, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 239 X(Reg_xmm12, 12, "xmm12", Reg_xmm12, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
239 NO_ALIASES()) \ 240 NO_ALIASES()) \
240 X(Reg_xmm13, 13, "xmm13", Reg_xmm13, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 241 X(Reg_xmm13, 13, "xmm13", Reg_xmm13, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
241 NO_ALIASES()) \ 242 NO_ALIASES()) \
242 X(Reg_xmm14, 14, "xmm14", Reg_xmm14, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 243 X(Reg_xmm14, 14, "xmm14", Reg_xmm14, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
243 NO_ALIASES()) \ 244 NO_ALIASES()) \
244 X(Reg_xmm15, 15, "xmm15", Reg_xmm15, 1,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \ 245 X(Reg_xmm15, 15, "xmm15", Reg_xmm15, 1,0,0,0,0, 0,0,0,0,0, 1, 0,0,0,0,0, \
245 NO_ALIASES()) \ 246 NO_ALIASES()) \
246 /* End of xmm register set */ 247 /* End of xmm register set */
247 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, 248 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
248 // isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8, 249 // sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8,
249 // isTrunc8Rcvr, isAhRcvr, aliases) 250 // is16To8, isTrunc8Rcvr, isAhRcvr, aliases)
250 251
251 // We also provide a combined table, so that there is a namespace where 252 // We also provide a combined table, so that there is a namespace where
252 // all of the registers are considered and have distinct numberings. 253 // all of the registers are considered and have distinct numberings.
253 // This is in contrast to the above, where the "encode" is based on how 254 // This is in contrast to the above, where the "encode" is based on how
254 // the register numbers will be encoded in binaries and values can overlap. 255 // the register numbers will be encoded in binaries and values can overlap.
255 #define REGX8664_TABLE \ 256 #define REGX8664_TABLE \
256 REGX8664_GPR_TABLE \ 257 REGX8664_GPR_TABLE \
257 REGX8664_XMM_TABLE 258 REGX8664_XMM_TABLE
258 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, 259 //#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,
259 // isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8, 260 // sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8,
260 // isTrunc8Rcvr, isAhRcvr, aliases) 261 // is16To8, isTrunc8Rcvr, isAhRcvr, aliases)
261 262
262 #define ICEINSTX8664BR_TABLE \ 263 #define ICEINSTX8664BR_TABLE \
263 /* val, encode, opposite, dump, emit */ \ 264 /* val, encode, opposite, dump, emit */ \
264 X(Br_o, 0, Br_no, "o", "jo") \ 265 X(Br_o, 0, Br_no, "o", "jo") \
265 X(Br_no, 1, Br_o, "no", "jno") \ 266 X(Br_no, 1, Br_o, "no", "jno") \
266 X(Br_b, 2, Br_ae, "b", "jb") \ 267 X(Br_b, 2, Br_ae, "b", "jb") \
267 X(Br_ae, 3, Br_b, "ae", "jae") \ 268 X(Br_ae, 3, Br_b, "ae", "jae") \
268 X(Br_e, 4, Br_ne, "e", "je") \ 269 X(Br_e, 4, Br_ne, "e", "je") \
269 X(Br_ne, 5, Br_e, "ne", "jne") \ 270 X(Br_ne, 5, Br_e, "ne", "jne") \
270 X(Br_be, 6, Br_a, "be", "jbe") \ 271 X(Br_be, 6, Br_a, "be", "jbe") \
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
304 X(v4i1, i32, "?", "", "", "", "d", "", "") \ 305 X(v4i1, i32, "?", "", "", "", "d", "", "") \
305 X(v8i1, i16, "?", "", "", "", "w", "", "") \ 306 X(v8i1, i16, "?", "", "", "", "w", "", "") \
306 X(v16i1, i8, "?", "", "", "", "b", "", "") \ 307 X(v16i1, i8, "?", "", "", "", "b", "", "") \
307 X(v16i8, i8, "?", "", "", "", "b", "", "") \ 308 X(v16i8, i8, "?", "", "", "", "b", "", "") \
308 X(v8i16, i16, "?", "", "", "", "w", "", "") \ 309 X(v8i16, i16, "?", "", "", "", "w", "", "") \
309 X(v4i32, i32, "dq", "", "", "", "d", "", "") \ 310 X(v4i32, i32, "dq", "", "", "", "d", "", "") \
310 X(v4f32, f32, "ps", "", "ps", "ps", "d", "", "") 311 X(v4f32, f32, "ps", "", "ps", "ps", "d", "", "")
311 //#define X(tag, elementty, cvt, sdss, pdps, pack, width, fld) 312 //#define X(tag, elementty, cvt, sdss, pdps, pack, width, fld)
312 313
313 #endif // SUBZERO_SRC_ICEINSTX8664_DEF 314 #endif // SUBZERO_SRC_ICEINSTX8664_DEF
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