Suzero. X8664. NaCl Sandboxing.

src/IceTargetLoweringX8632Traits.h

 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 416 matching lines @@
 
     template <typename T> struct __length<T> {
       static constexpr std::size_t value = 1;
     };
 
     const std::size_t Size;
   };
 
 public:
   static void initRegisterSet(
+      const ::Ice::ClFlags & /*Flags*/,
       std::array<llvm::SmallBitVector, RCX86_NUM> *TypeToRegisterSet,
       std::array<llvm::SmallBitVector, RegisterSet::Reg_NUM> *RegisterAliases,
       llvm::SmallBitVector *ScratchRegs) {
     llvm::SmallBitVector IntegerRegistersI32(RegisterSet::Reg_NUM);
     llvm::SmallBitVector IntegerRegistersI16(RegisterSet::Reg_NUM);
     llvm::SmallBitVector IntegerRegistersI8(RegisterSet::Reg_NUM);
     llvm::SmallBitVector FloatRegisters(RegisterSet::Reg_NUM);
     llvm::SmallBitVector VectorRegisters(RegisterSet::Reg_NUM);
     llvm::SmallBitVector Trunc64To8Registers(RegisterSet::Reg_NUM);
     llvm::SmallBitVector Trunc32To8Registers(RegisterSet::Reg_NUM);
@@ skipping 71 matching lines @@
     (*TypeToRegisterSet)[RC_v4i32] = VectorRegisters;
     (*TypeToRegisterSet)[RC_v4f32] = VectorRegisters;
     (*TypeToRegisterSet)[RCX86_Is64To8] = Trunc64To8Registers;
     (*TypeToRegisterSet)[RCX86_Is32To8] = Trunc32To8Registers;
     (*TypeToRegisterSet)[RCX86_Is16To8] = Trunc16To8Registers;
     (*TypeToRegisterSet)[RCX86_IsTrunc8Rcvr] = Trunc8RcvrRegisters;
     (*TypeToRegisterSet)[RCX86_IsAhRcvr] = AhRcvrRegisters;
   }
 
   static llvm::SmallBitVector
-  getRegisterSet(TargetLowering::RegSetMask Include,
+  getRegisterSet(const ::Ice::ClFlags & /*Flags*/,
+                 TargetLowering::RegSetMask Include,
                  TargetLowering::RegSetMask Exclude) {
     llvm::SmallBitVector Registers(RegisterSet::Reg_NUM);
 
 #define X(val, encode, name, base, scratch, preserved, stackptr, frameptr,     \
           isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8,      \
           isTrunc8Rcvr, isAhRcvr, aliases)                                     \
   if (scratch && (Include & ::Ice::TargetLowering::RegSet_CallerSave))         \
     Registers[RegisterSet::val] = true;                                        \
   if (preserved && (Include & ::Ice::TargetLowering::RegSet_CalleeSave))       \
     Registers[RegisterSet::val] = true;                                        \
@@ skipping 256 matching lines @@
       DefaultSegment = -1,
 #define X(val, name, prefix) val,
       SEG_REGX8632_TABLE
 #undef X
           SegReg_NUM
     };
     static X86OperandMem *create(Cfg *Func, Type Ty, Variable *Base,
                                  Constant *Offset, Variable *Index = nullptr,
                                  uint16_t Shift = 0,
                                  SegmentRegisters SegmentReg = DefaultSegment,
-                                 bool IsPIC = false) {
+                                 bool IsRebased = false) {
       return new (Func->allocate<X86OperandMem>()) X86OperandMem(
-          Func, Ty, Base, Offset, Index, Shift, SegmentReg, IsPIC);
+          Func, Ty, Base, Offset, Index, Shift, SegmentReg, IsRebased);
+    }
+    static X86OperandMem *create(Cfg *Func, Type Ty, Variable *Base,
+                                 Constant *Offset, bool IsRebased) {
+      constexpr Variable *NoIndex = nullptr;
+      constexpr uint16_t NoShift = 0;
+      return new (Func->allocate<X86OperandMem>()) X86OperandMem(
+          Func, Ty, Base, Offset, NoIndex, NoShift, DefaultSegment, IsRebased);
     }
     Variable *getBase() const { return Base; }
     Constant *getOffset() const { return Offset; }
     Variable *getIndex() const { return Index; }
     uint16_t getShift() const { return Shift; }
     SegmentRegisters getSegmentRegister() const { return SegmentReg; }
     void emitSegmentOverride(Assembler *Asm) const;
-    void setIsPIC() { IsPIC = true; }
-    bool getIsPIC() const { return IsPIC; }
-    Address toAsmAddress(Assembler *Asm,
-                         const Ice::TargetLowering *Target) const;
+    bool getIsRebased() const { return IsRebased; }
+    Address toAsmAddress(Assembler *Asm, const Ice::TargetLowering *Target,
+                         bool LeaAddr = false) const;
 
     void emit(const Cfg *Func) const override;
     using X86Operand::dump;
     void dump(const Cfg *Func, Ostream &Str) const override;
 
     static bool classof(const Operand *Operand) {
       return Operand->getKind() == static_cast<OperandKind>(kMem);
     }
 
     void setRandomized(bool R) { Randomized = R; }
 
     bool getRandomized() const { return Randomized; }
 
   private:
     X86OperandMem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset,
                   Variable *Index, uint16_t Shift, SegmentRegisters SegmentReg,
-                  bool IsPIC);
+                  bool IsRebased);
 
-    Variable *Base;
-    Constant *Offset;
-    Variable *Index;
-    uint16_t Shift;
-    SegmentRegisters SegmentReg : 16;
-    bool IsPIC;
+    Variable *const Base;
+    Constant *const Offset;
+    Variable *const Index;
+    const uint16_t Shift;
+    const SegmentRegisters SegmentReg : 16;
+    const bool IsRebased;
     /// A flag to show if this memory operand is a randomized one. Randomized
     /// memory operands are generated in
     /// TargetX86Base::randomizeOrPoolImmediate()
     bool Randomized = false;
   };
 
   /// VariableSplit is a way to treat an f64 memory location as a pair of i32
   /// locations (Low and High). This is needed for some cases of the Bitcast
   /// instruction. Since it's not possible for integer registers to access the
   /// XMM registers and vice versa, the lowering forces the f64 to be spilled to
@@ skipping 90 matching lines @@
 
   static uint8_t InstSegmentPrefixes[];
 };
 
 using Traits = ::Ice::X8632::TargetX8632Traits;
 } // end of namespace X8632
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H