Suzero. X8664. NaCl Sandboxing.

src/IceInstX86BaseImpl.h

 //===- subzero/src/IceInstX86BaseImpl.h - Generic X86 instructions -*- C++ -*=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 306 matching lines @@
     : InstX86Base(Func, InstX86Base::Pop, 0, Dest) {
   // A pop instruction affects the stack pointer and so it should not be
   // allowed to be automatically dead-code eliminated. (The corresponding push
   // instruction doesn't need this treatment because it has no dest variable
   // and therefore won't be dead-code eliminated.) This is needed for
   // late-stage liveness analysis (e.g. asm-verbose mode).
   this->HasSideEffects = true;
 }
 
 template <typename TraitsType>
-InstImpl<TraitsType>::InstX86Push::InstX86Push(Cfg *Func, Variable *Source)
+InstImpl<TraitsType>::InstX86Push::InstX86Push(Cfg *Func, Operand *Source)
     : InstX86Base(Func, InstX86Base::Push, 1, nullptr) {
   this->addSource(Source);
 }
 
 template <typename TraitsType>
+InstImpl<TraitsType>::InstX86Push::InstX86Push(Cfg *Func, InstX86Label *L)
+    : InstX86Base(Func, InstX86Base::Push, 0, nullptr), Label(L) {}
+
+template <typename TraitsType>
 InstImpl<TraitsType>::InstX86Ret::InstX86Ret(Cfg *Func, Variable *Source)
     : InstX86Base(Func, InstX86Base::Ret, Source ? 1 : 0, nullptr) {
   if (Source)
     this->addSource(Source);
 }
 
 template <typename TraitsType>
 InstImpl<TraitsType>::InstX86Setcc::InstX86Setcc(Cfg *Func, Variable *Dest,
                                                  BrCond Cond)
     : InstX86Base(Func, InstX86Base::Setcc, 0, Dest), Condition(Cond) {}
@@ skipping 105 matching lines @@
 void InstImpl<TraitsType>::InstX86Label::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << getName(Func) << ":";
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Label::emitIAS(const Cfg *Func) const {
   Assembler *Asm = Func->getAssembler<Assembler>();
+  if (IsReturnLocation) {
+    Asm->addRelocationAtCurrentPosition(getName(Func));
+  }
   Asm->bindLocalLabel(Number);
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Label::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << getName(Func) << ":";
 }
@@ skipping 77 matching lines @@
 
   Str << " // (" << (isNear() ? "near" : "far") << " jump)";
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Jmp::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 1);
+  const Operand *Src = this->getSrc(0);
+  if (Traits::Is64Bit) {
+    if (const auto *CR = llvm::dyn_cast<ConstantRelocatable>(Src)) {
+      Str << "\t"
+             "jmp"
+             "\t" << CR->getName();
+      return;
+    }
+  }
   Str << "\t"
-         "jmp\t*";
+         "jmp"
+         "\t*";
   getJmpTarget()->emit(Func);
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Jmp::emitIAS(const Cfg *Func) const {
   // Note: Adapted (mostly copied) from
   // InstImpl<TraitsType>::InstX86Call::emitIAS().
   Assembler *Asm = Func->getAssembler<Assembler>();
   Operand *Target = getJmpTarget();
   if (const auto *Var = llvm::dyn_cast<Variable>(Target)) {
@@ skipping 133 matching lines @@
   } else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Op)) {
     Mem->emitSegmentOverride(Asm);
     (Asm->*(Emitter.Addr))(Ty, Mem->toAsmAddress(Asm, Target));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <typename TraitsType>
 template <bool VarCanBeByte, bool SrcCanBeByte>
-void InstImpl<TraitsType>::emitIASRegOpTyGPR(const Cfg *Func, Type Ty,
-                                             const Variable *Var,
+void InstImpl<TraitsType>::emitIASRegOpTyGPR(const Cfg *Func, bool IsLea,
+                                             Type Ty, const Variable *Var,
                                              const Operand *Src,
                                              const GPREmitterRegOp &Emitter) {
   auto *Target = InstX86Base::getTarget(Func);
   Assembler *Asm = Func->getAssembler<Assembler>();
   assert(Var->hasReg());
   // We cheat a little and use GPRRegister even for byte operations.
   GPRRegister VarReg = VarCanBeByte ? Traits::getEncodedGPR(Var->getRegNum())
                                     : Traits::getEncodedGPR(Var->getRegNum());
   if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     if (SrcVar->hasReg()) {
       GPRRegister SrcReg = SrcCanBeByte
                                ? Traits::getEncodedGPR(SrcVar->getRegNum())
                                : Traits::getEncodedGPR(SrcVar->getRegNum());
       (Asm->*(Emitter.GPRGPR))(Ty, VarReg, SrcReg);
     } else {
       Address SrcStackAddr = Target->stackVarToAsmOperand(SrcVar);
       (Asm->*(Emitter.GPRAddr))(Ty, VarReg, SrcStackAddr);
     }
   } else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src)) {
     Mem->emitSegmentOverride(Asm);
-    (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Mem->toAsmAddress(Asm, Target));
+    (Asm->*(Emitter.GPRAddr))(Ty, VarReg,
+                              Mem->toAsmAddress(Asm, Target, IsLea));
   } else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
     (Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Imm->getValue()));
   } else if (const auto *Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
     AssemblerFixup *Fixup =
         Asm->createFixup(Traits::TargetLowering::getAbsFixup(), Reloc);
     (Asm->*(Emitter.GPRImm))(Ty, VarReg,
                              AssemblerImmediate(Reloc->getOffset(), Fixup));
   } else if (const auto *Split = llvm::dyn_cast<VariableSplit>(Src)) {
     (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Split->toAsmAddress(Func));
   } else {
@@ skipping 386 matching lines @@
     (void)Src0Var;
     assert(Src0Var->getRegNum() == RegisterSet::Reg_al);
     static const GPREmitterOneOp Emitter = {&Assembler::imul, &Assembler::imul};
     emitIASOpTyGPR(Func, Ty, this->getSrc(1), Emitter);
   } else {
     // The two-address version is used when multiplying by a non-constant
     // or doing an 8-bit multiply.
     assert(Var == this->getSrc(0));
     static const GPREmitterRegOp Emitter = {&Assembler::imul, &Assembler::imul,
                                             &Assembler::imul};
-    emitIASRegOpTyGPR(Func, Ty, Var, Src, Emitter);
+    constexpr bool NotLea = false;
+    emitIASRegOpTyGPR(Func, NotLea, Ty, Var, Src, Emitter);
   }
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86ImulImm::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 2);
   Variable *Dest = this->getDest();
@@ skipping 538 matching lines @@
   assert(this->getSrcSize() == 2);
   const Operand *Src0 = this->getSrc(0);
   const Operand *Src1 = this->getSrc(1);
   Type Ty = Src0->getType();
   static const GPREmitterRegOp RegEmitter = {&Assembler::cmp, &Assembler::cmp,
                                              &Assembler::cmp};
   static const GPREmitterAddrOp AddrEmitter = {&Assembler::cmp,
                                                &Assembler::cmp};
   if (const auto *SrcVar0 = llvm::dyn_cast<Variable>(Src0)) {
     if (SrcVar0->hasReg()) {
-      emitIASRegOpTyGPR(Func, Ty, SrcVar0, Src1, RegEmitter);
+      constexpr bool NotLea = false;
+      emitIASRegOpTyGPR(Func, NotLea, Ty, SrcVar0, Src1, RegEmitter);
       return;
     }
   }
   emitIASAsAddrOpTyGPR(Func, Ty, Src0, Src1, AddrEmitter);
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Icmp::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
@@ skipping 81 matching lines @@
   const Operand *Src0 = this->getSrc(0);
   const Operand *Src1 = this->getSrc(1);
   Type Ty = Src0->getType();
   // The Reg/Addr form of test is not encodeable.
   static const GPREmitterRegOp RegEmitter = {&Assembler::test, nullptr,
                                              &Assembler::test};
   static const GPREmitterAddrOp AddrEmitter = {&Assembler::test,
                                                &Assembler::test};
   if (const auto *SrcVar0 = llvm::dyn_cast<Variable>(Src0)) {
     if (SrcVar0->hasReg()) {
-      emitIASRegOpTyGPR(Func, Ty, SrcVar0, Src1, RegEmitter);
+      constexpr bool NotLea = false;
+      emitIASRegOpTyGPR(Func, NotLea, Ty, SrcVar0, Src1, RegEmitter);
       return;
     }
   }
   emitIASAsAddrOpTyGPR(Func, Ty, Src0, Src1, AddrEmitter);
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Test::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
@@ skipping 162 matching lines @@
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Lea::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 1);
   assert(this->getDest()->hasReg());
   Str << "\t"
-         "leal\t";
+         "lea" << this->getWidthString(this->getDest()->getType()) << "\t";
   Operand *Src0 = this->getSrc(0);
   if (const auto *Src0Var = llvm::dyn_cast<Variable>(Src0)) {
     Type Ty = Src0Var->getType();
     // lea on x86-32 doesn't accept mem128 operands, so cast VSrc0 to an
     // acceptable type.
     Src0Var->asType(isVectorType(Ty) ? IceType_i32 : Ty, Variable::NoRegister)
         ->emit(Func);
   } else {
     Src0->emit(Func);
   }
@@ skipping 79 matching lines @@
       if (Traits::Is64Bit && DestTy == IceType_i64) {
         if (const auto *C64 = llvm::dyn_cast<ConstantInteger64>(Src)) {
           Func->getAssembler<Assembler>()->movabs(
               Traits::getEncodedGPR(Dest->getRegNum()), C64->getValue());
           return;
         }
       }
       if (isScalarIntegerType(SrcTy)) {
         SrcTy = DestTy;
       }
-      emitIASRegOpTyGPR(Func, DestTy, Dest, Src, GPRRegEmitter);
+      constexpr bool NotLea = false;
+      emitIASRegOpTyGPR(Func, NotLea, DestTy, Dest, Src, GPRRegEmitter);
       return;
     }
   } else {
     // Dest must be Stack and Src *could* be a register. Use Src's type to
     // decide on the emitters.
     Address StackAddr(Target->stackVarToAsmOperand(Dest));
     if (isScalarFloatingType(SrcTy)) {
       // Src must be a register.
       const auto *SrcVar = llvm::cast<Variable>(Src);
       assert(SrcVar->hasReg());
@@ skipping 156 matching lines @@
 void InstImpl<TraitsType>::InstX86Movsx::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 1);
   const Variable *Dest = this->getDest();
   const Operand *Src = this->getSrc(0);
   // Dest must be a > 8-bit register, but Src can be 8-bit. In practice we just
   // use the full register for Dest to avoid having an OperandSizeOverride
   // prefix. It also allows us to only dispatch on SrcTy.
   Type SrcTy = Src->getType();
   assert(typeWidthInBytes(Dest->getType()) > 1);
   assert(typeWidthInBytes(Dest->getType()) > typeWidthInBytes(SrcTy));
-  emitIASRegOpTyGPR<false, true>(Func, SrcTy, Dest, Src, this->Emitter);
+  constexpr bool NotLea = false;
+  emitIASRegOpTyGPR<false, true>(Func, NotLea, SrcTy, Dest, Src, this->Emitter);
 }
 
 template <typename TraitsType>
+bool InstImpl<TraitsType>::InstX86Movzx::mayBeElided(
+    const Variable *Dest, const Operand *SrcOpnd) const {
+  assert(Traits::Is64Bit);
+  const auto *Src = llvm::dyn_cast<Variable>(SrcOpnd);
+
+  // Src is not a Variable, so it does not have a register. Movzx can't be
+  // elided.
+  if (Src == nullptr)
+    return false;
+
+  // Movzx to/from memory can't be elided.
+  if (!Src->hasReg() || !Dest->hasReg())
+    return false;
+
+  // Reg/reg move with different source and dest can't be elided.
+  if (Traits::getEncodedGPR(Src->getRegNum()) !=
+      Traits::getEncodedGPR(Dest->getRegNum()))
+    return false;
+
+  // A must-keep movzx 32- to 64-bit is sometimes needed in x86-64 sandboxing.
+  return !MustKeep;
+}
+
+template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Movzx::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   if (Traits::Is64Bit) {
     // There's no movzx %eXX, %rXX. To zero extend 32- to 64-bits, we emit a
     // mov %eXX, %eXX. The processor will still do a movzx[bw]q.
     assert(this->getSrcSize() == 1);
     const Operand *Src = this->getSrc(0);
     const Variable *Dest = this->Dest;
     if (Src->getType() == IceType_i32 && Dest->getType() == IceType_i64) {
       Ostream &Str = Func->getContext()->getStrEmit();
-      Str << "\t"
-             "mov"
-             "\t";
-      Src->emit(Func);
-      Str << ", ";
-      Dest->asType(IceType_i32,
-                   Traits::getGprForType(IceType_i32, Dest->getRegNum()))
-          ->emit(Func);
-      Str << " /* movzx */";
+      if (mayBeElided(Dest, Src)) {
+        Str << "\t/* elided movzx */";
+      } else {
+        Str << "\t"
+               "mov"
+               "\t";
+        Src->emit(Func);
+        Str << ", ";
+        Dest->asType(IceType_i32,
+                     Traits::getGprForType(IceType_i32, Dest->getRegNum()))
+            ->emit(Func);
+        Str << " /* movzx */";
+      }
       return;
     }
   }
   InstX86BaseUnaryopGPR<InstX86Base::Movzx>::emit(Func);
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Movzx::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 1);
   const Variable *Dest = this->getDest();
   const Operand *Src = this->getSrc(0);
   Type SrcTy = Src->getType();
   assert(typeWidthInBytes(Dest->getType()) > 1);
   assert(typeWidthInBytes(Dest->getType()) > typeWidthInBytes(SrcTy));
-  emitIASRegOpTyGPR<false, true>(Func, SrcTy, Dest, Src, this->Emitter);
+  if (Traits::Is64Bit) {

[Jim Stichnoth, 2016/01/14 00:09:52]

I would just add this to the && conjunction below and avoid nested ifs.

[John, 2016/01/14 23:18:25]

I thought about this, but I decided to go with this implementation because it
shows more clearly that the nested if is only applicable in x86-64. This is also
a somewhat common idiom throughout the code base (exception: boolean constant
initialization.)

+    if (Src->getType() == IceType_i32 && Dest->getType() == IceType_i64 &&
+        mayBeElided(Dest, Src)) {
+      return;
+    }
+  }
+  constexpr bool NotLea = false;
+  emitIASRegOpTyGPR<false, true>(Func, NotLea, SrcTy, Dest, Src, this->Emitter);
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Nop::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   // TODO: Emit the right code for each variant.
   Str << "\t"
          "nop\t/* variant = " << Variant << " */";
@@ skipping 301 matching lines @@
   Ostream &Str = Func->getContext()->getStrDump();
   this->dumpDest(Func);
   Str << " = pop." << this->getDest()->getType() << " ";
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Push::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
+  Str << "\t"
+         "push"
+         "\t";
   assert(this->getSrcSize() == 1);
-  // Push is currently only used for saving GPRs.
-  const auto *Var = llvm::cast<Variable>(this->getSrc(0));
-  assert(Var->hasReg());
-  Str << "\t"
-         "push\t";
-  Var->emit(Func);
+  const Operand *Src = this->getSrc(0);
+  Src->emit(Func);
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Push::emitIAS(const Cfg *Func) const {
+  Assembler *Asm = Func->getAssembler<Assembler>();
+
   assert(this->getSrcSize() == 1);
-  // Push is currently only used for saving GPRs.
-  const auto *Var = llvm::cast<Variable>(this->getSrc(0));
-  assert(Var->hasReg());
-  Assembler *Asm = Func->getAssembler<Assembler>();
-  Asm->pushl(Traits::getEncodedGPR(Var->getRegNum()));
+  const Operand *Src = this->getSrc(0);
+
+  if (const auto *Var = llvm::dyn_cast<Variable>(Src)) {
+    Asm->pushl(Traits::getEncodedGPR(Var->getRegNum()));
+  } else if (const auto *Const32 = llvm::dyn_cast<ConstantInteger32>(Src)) {
+    Asm->pushl(AssemblerImmediate(Const32->getValue()));
+  } else if (auto *CR = llvm::dyn_cast<ConstantRelocatable>(Src)) {
+    Asm->pushl(CR);
+  } else {
+    llvm_unreachable("Unexpected operand type");
+  }
 }
 
 template <typename TraitsType>
 void InstImpl<TraitsType>::InstX86Push::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "push." << this->getSrc(0)->getType() << " ";
   this->dumpSources(Func);
 }
@@ skipping 197 matching lines @@
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "IACA_END";
 }
 
 } // end of namespace X86NAMESPACE
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTX86BASEIMPL_H